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Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff
[linux-2.6.git]
/
arch
/
i386
/
kernel
/
cpu
/
cpufreq
/
cpufreq-nforce2.c
diff --git
a/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
b/arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
index
04a4053
..
f275e0d
100644
(file)
--- a/
arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
+++ b/
arch/i386/kernel/cpu/cpufreq/cpufreq-nforce2.c
@@
-39,7
+39,7
@@
static struct pci_dev *nforce2_chipset_dev;
static int fid = 0;
/* min_fsb, max_fsb:
static int fid = 0;
/* min_fsb, max_fsb:
- * minimum and maximum FSB (= FSB at boot time)
+ * minimum and maximum FSB (= FSB at boot time)
*/
static int min_fsb = 0;
static int max_fsb = 0;
*/
static int min_fsb = 0;
static int max_fsb = 0;
@@
-57,10
+57,10
@@
MODULE_PARM_DESC(min_fsb,
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "cpufreq-nforce2", msg)
-/*
+/*
*
* nforce2_calc_fsb - calculate FSB
* @pll: PLL value
* nforce2_calc_fsb - calculate FSB
* @pll: PLL value
- *
+ *
* Calculates FSB from PLL value
*/
static int nforce2_calc_fsb(int pll)
* Calculates FSB from PLL value
*/
static int nforce2_calc_fsb(int pll)
@@
-76,10
+76,10
@@
static int nforce2_calc_fsb(int pll)
return 0;
}
return 0;
}
-/*
+/*
*
* nforce2_calc_pll - calculate PLL value
* @fsb: FSB
* nforce2_calc_pll - calculate PLL value
* @fsb: FSB
- *
+ *
* Calculate PLL value for given FSB
*/
static int nforce2_calc_pll(unsigned int fsb)
* Calculate PLL value for given FSB
*/
static int nforce2_calc_pll(unsigned int fsb)
@@
-106,10
+106,10
@@
static int nforce2_calc_pll(unsigned int fsb)
return NFORCE2_PLL(mul, div);
}
return NFORCE2_PLL(mul, div);
}
-/*
+/*
*
* nforce2_write_pll - write PLL value to chipset
* @pll: PLL value
* nforce2_write_pll - write PLL value to chipset
* @pll: PLL value
- *
+ *
* Writes new FSB PLL value to chipset
*/
static void nforce2_write_pll(int pll)
* Writes new FSB PLL value to chipset
*/
static void nforce2_write_pll(int pll)
@@
-121,15
+121,13
@@
static void nforce2_write_pll(int pll)
pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
/* Now write the value in all 64 registers */
pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLADR, temp);
/* Now write the value in all 64 registers */
- for (temp = 0; temp <= 0x3f; temp++) {
- pci_write_config_dword(nforce2_chipset_dev,
- NFORCE2_PLLREG, pll);
- }
+ for (temp = 0; temp <= 0x3f; temp++)
+ pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
return;
}
return;
}
-/*
+/*
*
* nforce2_fsb_read - Read FSB
*
* Read FSB from chipset
* nforce2_fsb_read - Read FSB
*
* Read FSB from chipset
@@
-140,52
+138,46
@@
static unsigned int nforce2_fsb_read(int bootfsb)
struct pci_dev *nforce2_sub5;
u32 fsb, temp = 0;
struct pci_dev *nforce2_sub5;
u32 fsb, temp = 0;
-
/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
- 0x01EF,
- PCI_ANY_ID,
- PCI_ANY_ID,
- NULL);
-
+ 0x01EF,PCI_ANY_ID,PCI_ANY_ID,NULL);
if (!nforce2_sub5)
return 0;
pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
fsb /= 1000000;
if (!nforce2_sub5)
return 0;
pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
fsb /= 1000000;
-
+
/* Check if PLL register is already set */
/* Check if PLL register is already set */
- pci_read_config_byte(nforce2_chipset_dev,
- NFORCE2_PLLENABLE, (u8 *)&temp);
-
+ pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
+
if(bootfsb || !temp)
return fsb;
/* Use PLL register FSB value */
if(bootfsb || !temp)
return fsb;
/* Use PLL register FSB value */
- pci_read_config_dword(nforce2_chipset_dev,
- NFORCE2_PLLREG, &temp);
+ pci_read_config_dword(nforce2_chipset_dev,NFORCE2_PLLREG, &temp);
fsb = nforce2_calc_fsb(temp);
return fsb;
}
fsb = nforce2_calc_fsb(temp);
return fsb;
}
-/*
+/*
*
* nforce2_set_fsb - set new FSB
* @fsb: New FSB
* nforce2_set_fsb - set new FSB
* @fsb: New FSB
- *
+ *
* Sets new FSB
*/
static int nforce2_set_fsb(unsigned int fsb)
{
* Sets new FSB
*/
static int nforce2_set_fsb(unsigned int fsb)
{
- u32
pll,
temp = 0;
+ u32 temp = 0;
unsigned int tfsb;
int diff;
unsigned int tfsb;
int diff;
+ int pll = 0;
if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
return -EINVAL;
}
if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
printk(KERN_ERR "cpufreq: FSB %d is out of range!\n", fsb);
return -EINVAL;
}
-
+
tfsb = nforce2_fsb_read(0);
if (!tfsb) {
printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
tfsb = nforce2_fsb_read(0);
if (!tfsb) {
printk(KERN_ERR "cpufreq: Error while reading the FSB\n");
@@
-193,8
+185,7
@@
static int nforce2_set_fsb(unsigned int fsb)
}
/* First write? Then set actual value */
}
/* First write? Then set actual value */
- pci_read_config_byte(nforce2_chipset_dev,
- NFORCE2_PLLENABLE, (u8 *)&temp);
+ pci_read_config_byte(nforce2_chipset_dev,NFORCE2_PLLENABLE, (u8 *)&temp);
if (!temp) {
pll = nforce2_calc_pll(tfsb);
if (!temp) {
pll = nforce2_calc_pll(tfsb);
@@
-222,7
+213,7
@@
static int nforce2_set_fsb(unsigned int fsb)
/* Calculate the PLL reg. value */
if ((pll = nforce2_calc_pll(tfsb)) == -1)
return -EINVAL;
/* Calculate the PLL reg. value */
if ((pll = nforce2_calc_pll(tfsb)) == -1)
return -EINVAL;
-
+
nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
mdelay(NFORCE2_DELAY);
nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
mdelay(NFORCE2_DELAY);
@@
-238,7
+229,7
@@
static int nforce2_set_fsb(unsigned int fsb)
/**
* nforce2_get - get the CPU frequency
* @cpu: CPU number
/**
* nforce2_get - get the CPU frequency
* @cpu: CPU number
- *
+ *
* Returns the CPU frequency
*/
static unsigned int nforce2_get(unsigned int cpu)
* Returns the CPU frequency
*/
static unsigned int nforce2_get(unsigned int cpu)
@@
-353,10
+344,10
@@
static int nforce2_cpu_init(struct cpufreq_policy *policy)
printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
fid / 10, fid % 10);
printk(KERN_INFO "cpufreq: FSB currently at %i MHz, FID %d.%d\n", fsb,
fid / 10, fid % 10);
-
+
/* Set maximum FSB to FSB at boot time */
max_fsb = nforce2_fsb_read(1);
/* Set maximum FSB to FSB at boot time */
max_fsb = nforce2_fsb_read(1);
-
+
if(!max_fsb)
return -EIO;
if(!max_fsb)
return -EIO;
@@
-397,17
+388,15
@@
static struct cpufreq_driver nforce2_driver = {
* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
*
* Detects nForce2 A2 and C1 stepping
* nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
*
* Detects nForce2 A2 and C1 stepping
- *
+ *
*/
static unsigned int nforce2_detect_chipset(void)
{
u8 revision;
nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
*/
static unsigned int nforce2_detect_chipset(void)
{
u8 revision;
nforce2_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_NFORCE2,
- PCI_ANY_ID,
- PCI_ANY_ID,
- NULL);
+ PCI_DEVICE_ID_NVIDIA_NFORCE2,
+ PCI_ANY_ID, PCI_ANY_ID, NULL);
if (nforce2_chipset_dev == NULL)
return -ENODEV;
if (nforce2_chipset_dev == NULL)
return -ENODEV;