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fedora core 6 1.2949 + vserver 2.2.0
[linux-2.6.git]
/
arch
/
i386
/
kernel
/
cpu
/
intel.c
diff --git
a/arch/i386/kernel/cpu/intel.c
b/arch/i386/kernel/cpu/intel.c
index
8c01201
..
56fe265
100644
(file)
--- a/
arch/i386/kernel/cpu/intel.c
+++ b/
arch/i386/kernel/cpu/intel.c
@@
-1,4
+1,3
@@
-#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/kernel.h>
@@
-29,7
+28,7
@@
extern int trap_init_f00f_bug(void);
struct movsl_mask movsl_mask __read_mostly;
#endif
struct movsl_mask movsl_mask __read_mostly;
#endif
-void __
dev
init early_intel_workaround(struct cpuinfo_x86 *c)
+void __
cpu
init early_intel_workaround(struct cpuinfo_x86 *c)
{
if (c->x86_vendor != X86_VENDOR_INTEL)
return;
{
if (c->x86_vendor != X86_VENDOR_INTEL)
return;
@@
-44,7
+43,7
@@
void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
* This is called before we do cpu ident work
*/
* This is called before we do cpu ident work
*/
-int __
dev
init ppro_with_ram_bug(void)
+int __
cpu
init ppro_with_ram_bug(void)
{
/* Uses data from early_cpu_detect now */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
{
/* Uses data from early_cpu_detect now */
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
@@
-62,7
+61,7
@@
int __devinit ppro_with_ram_bug(void)
* P4 Xeon errata 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
*/
* P4 Xeon errata 037 workaround.
* Hardware prefetcher may cause stale data to be loaded into the cache.
*/
-static void __
dev
init Intel_errata_workarounds(struct cpuinfo_x86 *c)
+static void __
cpu
init Intel_errata_workarounds(struct cpuinfo_x86 *c)
{
unsigned long lo, hi;
{
unsigned long lo, hi;
@@
-81,7
+80,7
@@
static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
/*
* find out the number of processor cores on the die
*/
/*
* find out the number of processor cores on the die
*/
-static int __
dev
init num_cpu_cores(struct cpuinfo_x86 *c)
+static int __
cpu
init num_cpu_cores(struct cpuinfo_x86 *c)
{
unsigned int eax, ebx, ecx, edx;
{
unsigned int eax, ebx, ecx, edx;
@@
-96,7
+95,7
@@
static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
return 1;
}
return 1;
}
-static void __
dev
init init_intel(struct cpuinfo_x86 *c)
+static void __
cpu
init init_intel(struct cpuinfo_x86 *c)
{
unsigned int l2 = 0;
char *p = NULL;
{
unsigned int l2 = 0;
char *p = NULL;
@@
-108,7
+107,7
@@
static void __devinit init_intel(struct cpuinfo_x86 *c)
* Note that the workaround only should be initialized once...
*/
c->f00f_bug = 0;
* Note that the workaround only should be initialized once...
*/
c->f00f_bug = 0;
- if (
c->x86 == 5
) {
+ if (
!paravirt_enabled() && c->x86 == 5
) {
static int f00f_workaround_enabled = 0;
c->f00f_bug = 1;
static int f00f_workaround_enabled = 0;
c->f00f_bug = 1;
@@
-122,6
+121,12
@@
static void __devinit init_intel(struct cpuinfo_x86 *c)
select_idle_routine(c);
l2 = init_intel_cacheinfo(c);
select_idle_routine(c);
l2 = init_intel_cacheinfo(c);
+ if (c->cpuid_level > 9 ) {
+ unsigned eax = cpuid_eax(10);
+ /* Check for version and the number of counters */
+ if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
+ set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
+ }
/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
/* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
@@
-190,10
+195,18
@@
static void __devinit init_intel(struct cpuinfo_x86 *c)
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
(c->x86 == 0x6 && c->x86_model >= 0x0e))
set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
-}
+ if (cpu_has_ds) {
+ unsigned int l1;
+ rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
+ if (!(l1 & (1<<11)))
+ set_bit(X86_FEATURE_BTS, c->x86_capability);
+ if (!(l1 & (1<<12)))
+ set_bit(X86_FEATURE_PEBS, c->x86_capability);
+ }
+}
-static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int
__cpuinit
intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
{
/* Intel PIII Tualatin. This comes in two flavours.
* One has 256kb of cache, the other 512. We have no way
{
/* Intel PIII Tualatin. This comes in two flavours.
* One has 256kb of cache, the other 512. We have no way
@@
-205,7
+218,7
@@
static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
return size;
}
return size;
}
-static struct cpu_dev intel_cpu_dev __
dev
initdata = {
+static struct cpu_dev intel_cpu_dev __
cpu
initdata = {
.c_vendor = "Intel",
.c_ident = { "GenuineIntel" },
.c_models = {
.c_vendor = "Intel",
.c_ident = { "GenuineIntel" },
.c_models = {
@@
-258,7
+271,6
@@
static struct cpu_dev intel_cpu_dev __devinitdata = {
},
},
.c_init = init_intel,
},
},
.c_init = init_intel,
- .c_identify = generic_identify,
.c_size_cache = intel_size_cache,
};
.c_size_cache = intel_size_cache,
};