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Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff
[linux-2.6.git]
/
arch
/
ia64
/
sn
/
pci
/
pcibr
/
pcibr_reg.c
diff --git
a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index
74a74a7
..
8b8bbd5
100644
(file)
--- a/
arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/
arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@
-6,13
+6,14
@@
* Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
*/
* Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
*/
-#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/interrupt.h>
-#include "pci/pcibus_provider_defs.h"
-#include "pci/pcidev.h"
-#include "pci/tiocp.h"
-#include "pci/pic.h"
-#include "pci/pcibr_provider.h"
+#include <linux/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/pcibr_provider.h>
+#include <asm/sn/pcibus_provider_defs.h>
+#include <asm/sn/pcidev.h>
+#include <asm/sn/pic.h>
+#include <asm/sn/tiocp.h>
union br_ptr {
struct tiocp tio;
union br_ptr {
struct tiocp tio;
@@
-22,42
+23,42
@@
union br_ptr {
/*
* Control Register Access -- Read/Write 0000_0020
*/
/*
* Control Register Access -- Read/Write 0000_0020
*/
-void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u
int64_t
bits)
+void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u
64
bits)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_control &= ~bits
;
+
__sn_clrq_relaxed(&ptr->tio.cp_control, bits)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_wid_control &= ~bits
;
+
__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits)
;
break;
default:
panic
("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
-void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u
int64_t
bits)
+void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u
64
bits)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_control |= bits
;
+
__sn_setq_relaxed(&ptr->tio.cp_control, bits)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_wid_control |= bits
;
+
__sn_setq_relaxed(&ptr->pic.p_wid_control, bits)
;
break;
default:
panic
("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
@@
-65,23
+66,23
@@
void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
/*
* PCI/PCIX Target Flush Register Access -- Read Only 0000_0050
*/
/*
* PCI/PCIX Target Flush Register Access -- Read Only 0000_0050
*/
-u
int64_t
pcireg_tflush_get(struct pcibus_info *pcibus_info)
+u
64
pcireg_tflush_get(struct pcibus_info *pcibus_info)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
- u
int64_t
ret = 0;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
+ u
64
ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
- ret =
ptr->tio.cp_tflush
;
+ ret =
__sn_readq_relaxed(&ptr->tio.cp_tflush)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
- ret =
ptr->pic.p_wid_tflush
;
+ ret =
__sn_readq_relaxed(&ptr->pic.p_wid_tflush)
;
break;
default:
panic
("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
@@
-95,23
+96,23
@@
uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
/*
* Interrupt Status Register Access -- Read Only 0000_0100
*/
/*
* Interrupt Status Register Access -- Read Only 0000_0100
*/
-u
int64_t
pcireg_intr_status_get(struct pcibus_info * pcibus_info)
+u
64
pcireg_intr_status_get(struct pcibus_info * pcibus_info)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
- u
int64_t
ret = 0;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
+ u
64
ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
- ret =
ptr->tio.cp_int_status
;
+ ret =
__sn_readq_relaxed(&ptr->tio.cp_int_status)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
- ret =
ptr->pic.p_int_status
;
+ ret =
__sn_readq_relaxed(&ptr->pic.p_int_status)
;
break;
default:
panic
("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
return ret;
}
}
return ret;
@@
-120,42
+121,42
@@
uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
/*
* Interrupt Enable Register Access -- Read/Write 0000_0108
*/
/*
* Interrupt Enable Register Access -- Read/Write 0000_0108
*/
-void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u
int64_t
bits)
+void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u
64
bits)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_int_enable &= ~bits
;
+
__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_int_enable &= ~bits
;
+
__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits)
;
break;
default:
panic
("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
-void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u
int64_t
bits)
+void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u
64
bits)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_int_enable |= bits
;
+
__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits)
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_int_enable |= bits
;
+
__sn_setq_relaxed(&ptr->pic.p_int_enable, bits)
;
break;
default:
panic
("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
@@
-164,26
+165,28
@@
void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
* Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168
*/
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
* Intr Host Address Register (int_addr) -- Read/Write 0000_0130 - 0000_0168
*/
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
- u
int64_t
addr)
+ u
64
addr)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
- ptr->tio.cp_int_addr[int_n] &= ~TIOCP_HOST_INTR_ADDR;
- ptr->tio.cp_int_addr[int_n] |=
- (addr & TIOCP_HOST_INTR_ADDR);
+ __sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
+ TIOCP_HOST_INTR_ADDR);
+ __sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
+ (addr & TIOCP_HOST_INTR_ADDR));
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
- ptr->pic.p_int_addr[int_n] &= ~PIC_HOST_INTR_ADDR;
- ptr->pic.p_int_addr[int_n] |=
- (addr & PIC_HOST_INTR_ADDR);
+ __sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
+ PIC_HOST_INTR_ADDR);
+ __sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
+ (addr & PIC_HOST_INTR_ADDR));
break;
default:
panic
("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
@@
-193,20
+196,20
@@
void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
*/
void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
{
*/
void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_force_pin[int_n] = 1
;
+
writeq(1, &ptr->tio.cp_force_pin[int_n])
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_force_pin[int_n] = 1
;
+
writeq(1, &ptr->pic.p_force_pin[int_n])
;
break;
default:
panic
("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
@@
-214,21
+217,23
@@
void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
/*
* Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
*/
/*
* Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
*/
-u
int64_t
pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
+u
64
pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
- u
int64_t
ret = 0;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
+ u
64
ret = 0;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
- ret = ptr->tio.cp_wr_req_buf[device];
+ ret =
+ __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
- ret = ptr->pic.p_wr_req_buf[device];
+ ret =
+ __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
break;
default:
break;
default:
- panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p",
(void *)
ptr);
+ panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
}
}
}
}
@@
-237,45
+242,43
@@
uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
}
void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
}
void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
- u
int64_t
val)
+ u
64
val)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
-
ptr->tio.cp_int_ate_ram[ate_index] = (uint64_t) val
;
+
writeq(val, &ptr->tio.cp_int_ate_ram[ate_index])
;
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
-
ptr->pic.p_int_ate_ram[ate_index] = (uint64_t) val
;
+
writeq(val, &ptr->pic.p_int_ate_ram[ate_index])
;
break;
default:
panic
("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
}
}
}
}
-u
int64_t
*pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
+u
64 __iomem
*pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
{
{
- union br_ptr
*ptr = (union br_ptr
*)pcibus_info->pbi_buscommon.bs_base;
- u
int64_t *ret = (uint64_t *) 0
;
+ union br_ptr
__iomem *ptr = (union br_ptr __iomem
*)pcibus_info->pbi_buscommon.bs_base;
+ u
64 __iomem *ret = NULL
;
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
if (pcibus_info) {
switch (pcibus_info->pbi_bridge_type) {
case PCIBR_BRIDGETYPE_TIOCP:
- ret =
- (uint64_t *) & (ptr->tio.cp_int_ate_ram[ate_index]);
+ ret = &ptr->tio.cp_int_ate_ram[ate_index];
break;
case PCIBR_BRIDGETYPE_PIC:
break;
case PCIBR_BRIDGETYPE_PIC:
- ret =
- (uint64_t *) & (ptr->pic.p_int_ate_ram[ate_index]);
+ ret = &ptr->pic.p_int_ate_ram[ate_index];
break;
default:
panic
("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
break;
default:
panic
("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
-
(void *)
ptr);
+ ptr);
}
}
return ret;
}
}
return ret;