+ /* atomic operation:
+ * oldval = *addr; *addr = 1;
+ */
+ __asm__ __volatile__ (
+ DCACHE_CLEAR("%0", "r4", "%1")
+ " .fillinsn\n"
+ "1:\n"
+ " lock %0, @%1 -> unlock %2, @%1\n"
+ "2:\n"
+ /* NOTE:
+ * The m32r processor can accept interrupts only
+ * at the 32-bit instruction boundary.
+ * So, in the above code, the "unlock" instruction
+ * can be executed continuously after the "lock"
+ * instruction execution without any interruptions.
+ */
+ ".section .fixup,\"ax\"\n"
+ " .balign 4\n"
+ "3: ldi %0, #%3\n"
+ " seth r14, #high(2b)\n"
+ " or3 r14, r14, #low(2b)\n"
+ " jmp r14\n"
+ ".previous\n"
+ ".section __ex_table,\"a\"\n"
+ " .balign 4\n"
+ " .long 1b,3b\n"
+ ".previous\n"
+ : "=&r" (oldval)
+ : "r" (addr), "r" (1), "i"(-EFAULT)
+ : "r14", "memory"
+#ifdef CONFIG_CHIP_M32700_TS1
+ , "r4"
+#endif /* CONFIG_CHIP_M32700_TS1 */
+ );