-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
RES_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package
| actual or intended publication of such source code.
RES_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
-| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
+| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
cu_nmrd:
movel #2,%d0 |set up the size for denorm
movew LOCAL_EX(%a0),%d1 |compare exponent to double threshold
cu_nmrd:
movel #2,%d0 |set up the size for denorm
movew LOCAL_EX(%a0),%d1 |compare exponent to double threshold
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
-| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
+| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
- bra cu_dnrm |fmove, fabs, fneg, ftst
+ bra cu_dnrm |fmove, fabs, fneg, ftst
|
| cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and
|
| cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and
bra cu_sndr |load single neg zero w/lsb
|
| The precision is extended, so the result in etemp is correct.
bra cu_sndr |load single neg zero w/lsb
|
| The precision is extended, so the result in etemp is correct.
| the correct fp register.
cu_wrexd:
orl #unfl_mask,USER_FPSR(%a6)
| the correct fp register.
cu_wrexd:
orl #unfl_mask,USER_FPSR(%a6)
orl #neg_mask,USER_FPSR(%a6)
orl #unfinx_mask,USER_FPSR(%a6)
bra wr_etemp
orl #neg_mask,USER_FPSR(%a6)
orl #unfinx_mask,USER_FPSR(%a6)
bra wr_etemp
|
| This code checks for 16-bit overflow conditions on dyadic
| operations which are not restorable into the floating-point
|
| This code checks for 16-bit overflow conditions on dyadic
| operations which are not restorable into the floating-point
| $ff for both ops denormalized
|
| The wrap-around condition occurs for add, sub, div, and cmp
| $ff for both ops denormalized
|
| The wrap-around condition occurs for add, sub, div, and cmp
| for this condition. The restore flag (RES_FLG) is left clear.
| No frestore is done unless an exception is to be reported.
|
| for this condition. The restore flag (RES_FLG) is left clear.
| No frestore is done unless an exception is to be reported.
|
| if(sign_of(dest) != sign_of(src))
| replace exponent of src with $3fff (keep sign)
| use fpu to perform dest+new_src (user's rmode and X)
| if(sign_of(dest) != sign_of(src))
| replace exponent of src with $3fff (keep sign)
| use fpu to perform dest+new_src (user's rmode and X)
andib #0x60,%d0 |isolate tag bits
cmpb #0x40,%d0 |is it inf?
beq nan_or_inf |not wrap case
andib #0x60,%d0 |isolate tag bits
cmpb #0x40,%d0 |is it inf?
beq nan_or_inf |not wrap case
| ;sets FPSR_CC correctly
| ;returns in external format
bfclr WBTEMP_SGN(%a6){#0:#8}
| ;sets FPSR_CC correctly
| ;returns in external format
bfclr WBTEMP_SGN(%a6){#0:#8}
beq force_unf |force an underflow (really!)
|
| One of the ops is denormalized. Test for wrap condition
beq force_unf |force an underflow (really!)
|
| One of the ops is denormalized. Test for wrap condition
bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg)
addl %d1,%d0 |subtract src from dest
bgt fix_stk
bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg)
addl %d1,%d0 |subtract src from dest
bgt fix_stk
bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec
frcunf_rnd:
bsrl unf_sub |get correct result based on
bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec
frcunf_rnd:
bsrl unf_sub |get correct result based on
bclrb #sign_bit,WBTEMP_EX(%a6)
sne WBTEMP_SGN(%a6)
bsrl ovf_res |get correct result based on
bclrb #sign_bit,WBTEMP_EX(%a6)
sne WBTEMP_SGN(%a6)
bsrl ovf_res |get correct result based on
| ;sets FPSR_CC correctly
bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format
beqs frcfpn_clr
bsetb #sign_bit,WBTEMP_EX(%a6)
frcfpn_clr:
orl #ovfinx_mask,USER_FPSR(%a6)
| ;sets FPSR_CC correctly
bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format
beqs frcfpn_clr
bsetb #sign_bit,WBTEMP_EX(%a6)
frcfpn_clr:
orl #ovfinx_mask,USER_FPSR(%a6)
frc3_dst:
movel WBTEMP_EX(%a6),USER_FP3(%a6)
movel WBTEMP_HI(%a6),USER_FP3+4(%a6)
frc3_dst:
movel WBTEMP_EX(%a6),USER_FP3(%a6)
movel WBTEMP_HI(%a6),USER_FP3+4(%a6)
beqs fmoveinc |enabled, force restore
btstb #snan_bit,FPCR_ENABLE(%a6) |and don't overwrite
beqs fmoveinc |the dest
beqs fmoveinc |enabled, force restore
btstb #snan_bit,FPCR_ENABLE(%a6) |and don't overwrite
beqs fmoveinc |the dest
cmpib #0x60,%d0 |check if stag is NaN
bnes fminc_czero
orl #nan_mask,USER_FPSR(%a6) |if nan, nothing yet has set NaN
cmpib #0x60,%d0 |check if stag is NaN
bnes fminc_czero
orl #nan_mask,USER_FPSR(%a6) |if nan, nothing yet has set NaN
fp3_dst:
movel ETEMP_EX(%a6),USER_FP3(%a6)
movel ETEMP_HI(%a6),USER_FP3+4(%a6)
fp3_dst:
movel ETEMP_EX(%a6),USER_FP3(%a6)
movel ETEMP_HI(%a6),USER_FP3+4(%a6)
fmovemx ETEMP(%a6),%fp0-%fp0
fcmpd #0x41dfffffffc00000,%fp0
| 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec
fmovemx ETEMP(%a6),%fp0-%fp0
fcmpd #0x41dfffffffc00000,%fp0
| 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec
fcmpd #0xc1e0000000000000,%fp0
| c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec
fble lo_nlrg
fcmpd #0xc1e0000000000000,%fp0
| c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec
fble lo_nlrg
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x46fffe00,%fp0
| 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x46fffe00,%fp0
| 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x42fe0000,%fp0
| 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x42fe0000,%fp0
| 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec
int_dnrm:
movel #0,L_SCR1(%a6) | initialize result to 0
bfextu FPCR_MODE(%a6){#2:#2},%d1 | d1 is the rounding mode
int_dnrm:
movel #0,L_SCR1(%a6) | initialize result to 0
bfextu FPCR_MODE(%a6){#2:#2},%d1 | d1 is the rounding mode
bmis int_inx | if RN or RZ, done
bnes int_rp | if RP, continue below
tstw ETEMP(%a6) | RM: store -1 in L_SCR1 if src is negative
bmis int_inx | if RN or RZ, done
bnes int_rp | if RP, continue below
tstw ETEMP(%a6) | RM: store -1 in L_SCR1 if src is negative
bmis int_inx | otherwise, result is 0
lea L_SCR1(%a6),%a1 | a1 is address of L_SCR1
addal %d0,%a1 | offset by destination width -1
bmis int_inx | otherwise, result is 0
lea L_SCR1(%a6),%a1 | a1 is address of L_SCR1
addal %d0,%a1 | offset by destination width -1
bsetb #0,(%a1) | set low bit at a1 address
int_inx:
oril #inx2a_mask,USER_FPSR(%a6)
bsetb #0,(%a1) | set low bit at a1 address
int_inx:
oril #inx2a_mask,USER_FPSR(%a6)
oril #opaop_mask,USER_FPSR(%a6)
| ;fall through to perform int_wrt
oril #opaop_mask,USER_FPSR(%a6)
| ;fall through to perform int_wrt
movel EXC_EA(%a6),%a1 |load destination address
tstl %a1 |check to see if it is a dest register
movel EXC_EA(%a6),%a1 |load destination address
tstl %a1 |check to see if it is a dest register
sz_con:
movel %d0,%d1 |reg_dest expects size:reg in d1
bsrl reg_dest |load proper data register
sz_con:
movel %d0,%d1 |reg_dest expects size:reg in d1
bsrl reg_dest |load proper data register
bfextu FPCR_MODE(%a6){#2:#2},%d1 |rnd mode in d1
swap %d0 |rnd prec in upper word
addl %d0,%d1 |d1 has PREC/MODE info
bfextu FPCR_MODE(%a6){#2:#2},%d1 |rnd mode in d1
swap %d0 |rnd prec in upper word
addl %d0,%d1 |d1 has PREC/MODE info
bsrl dest_ext |store to memory
bsetb #unfl_bit,FPSR_EXCEPT(%a6)
bra mvout_end
bsrl dest_ext |store to memory
bsetb #unfl_bit,FPSR_EXCEPT(%a6)
bra mvout_end
movel #1,%d0 |load in round precision
movel #sgl_thresh,%d1 |load in single denorm threshold
movel #1,%d0 |load in round precision
movel #sgl_thresh,%d1 |load in single denorm threshold
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
bsrl dest_sgl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
bsrl dest_sgl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
dp_catas:
| Temp fix for z bit set in unf_sub
movel USER_FPSR(%a6),-(%a7)
dp_catas:
| Temp fix for z bit set in unf_sub
movel USER_FPSR(%a6),-(%a7)
| ;denorm/norm bias
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
| ;denorm/norm bias
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
bsrl dest_dbl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
bsrl dest_dbl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
|
| This subroutine takes an extended normalized number and denormalizes
| it to the given round precision. This subroutine also decrements
|
| This subroutine takes an extended normalized number and denormalizes
| it to the given round precision. This subroutine also decrements
swap %d1 |at this point d1 has PREC/MODE info
bsrl round |round result, sets the inex bit in
| ;USER_FPSR if needed
swap %d1 |at this point d1 has PREC/MODE info
bsrl round |round result, sets the inex bit in
| ;USER_FPSR if needed
movew STAG(%a6),%d0 |get source tag
bfextu %d0{#16:#3},%d0 |isolate source bits
movel (%a0,%d0.w*4),%a0 |load a0 with routine label for tag
jmp (%a0) |go to the routine
p_write:
movew STAG(%a6),%d0 |get source tag
bfextu %d0{#16:#3},%d0 |isolate source bits
movel (%a0,%d0.w*4),%a0 |load a0 with routine label for tag
jmp (%a0) |go to the routine
p_write: