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Revert to Fedora kernel-2.6.17-1.2187_FC5 patched with vs2.0.2.1; there are too many...
[linux-2.6.git]
/
arch
/
mips
/
kernel
/
ptrace32.c
diff --git
a/arch/mips/kernel/ptrace32.c
b/arch/mips/kernel/ptrace32.c
index
f40ecd8
..
8704dc0
100644
(file)
--- a/
arch/mips/kernel/ptrace32.c
+++ b/
arch/mips/kernel/ptrace32.c
@@
-166,7
+166,10
@@
asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
tmp = regs->lo;
break;
case FPC_CSR:
tmp = regs->lo;
break;
case FPC_CSR:
- tmp = child->thread.fpu.fcr31;
+ if (cpu_has_fpu)
+ tmp = child->thread.fpu.hard.fcr31;
+ else
+ tmp = child->thread.fpu.soft.fcr31;
break;
case FPC_EIR: { /* implementation / version register */
unsigned int flags;
break;
case FPC_EIR: { /* implementation / version register */
unsigned int flags;
@@
-285,9
+288,9
@@
asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
if (!tsk_used_math(child)) {
/* FP not yet used */
if (!tsk_used_math(child)) {
/* FP not yet used */
- memset(&child->thread.fpu, ~0,
- sizeof(child->thread.fpu));
- child->thread.fpu.fcr31 = 0;
+ memset(&child->thread.fpu
.hard
, ~0,
+ sizeof(child->thread.fpu
.hard
));
+ child->thread.fpu.
hard.
fcr31 = 0;
}
/*
* The odd registers are actually the high order bits
}
/*
* The odd registers are actually the high order bits
@@
-315,7
+318,10
@@
asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
regs->lo = data;
break;
case FPC_CSR:
regs->lo = data;
break;
case FPC_CSR:
- child->thread.fpu.fcr31 = data;
+ if (cpu_has_fpu)
+ child->thread.fpu.hard.fcr31 = data;
+ else
+ child->thread.fpu.soft.fcr31 = data;
break;
case DSP_BASE ... DSP_BASE + 5: {
dspreg_t *dregs;
break;
case DSP_BASE ... DSP_BASE + 5: {
dspreg_t *dregs;