+#ifdef CONFIG_MIPS_MT_SMTC
+ /*
+ * In an SMTC system, one Count/Compare set exists per VPE.
+ * Which TC within a VPE gets the interrupt is essentially
+ * random - we only know that it shouldn't be one with
+ * IXMT set. Whichever TC gets the interrupt needs to
+ * send special interprocessor interrupts to the other
+ * TCs to make sure that they schedule, etc.
+ *
+ * That code is specific to the SMTC kernel, not to
+ * the a particular platform, so it's invoked from
+ * the general MIPS timer_interrupt routine.
+ */
+
+ int vpflags;
+
+ /*
+ * We could be here due to timer interrupt,
+ * perf counter overflow, or both.
+ */
+ if (read_c0_cause() & (1 << 26))
+ perf_irq();
+
+ if (read_c0_cause() & (1 << 30)) {
+ /* If timer interrupt, make it de-assert */
+ write_c0_compare (read_c0_count() - 1);
+ /*
+ * DVPE is necessary so long as cross-VPE interrupts
+ * are done via read-modify-write of Cause register.
+ */
+ vpflags = dvpe();
+ clear_c0_cause(CPUCTR_IMASKBIT);
+ evpe(vpflags);
+ /*
+ * There are things we only want to do once per tick
+ * in an "MP" system. One TC of each VPE will take
+ * the actual timer interrupt. The others will get
+ * timer broadcast IPIs. We use whoever it is that takes
+ * the tick on VPE 0 to run the full timer_interrupt().
+ */
+ if (cpu_data[cpu].vpe_id == 0) {
+ timer_interrupt(irq, NULL);
+ smtc_timer_broadcast(cpu_data[cpu].vpe_id);
+ scroll_display_message();
+ } else {
+ write_c0_compare(read_c0_count() +
+ (mips_hpt_frequency/HZ));
+ local_timer_interrupt(irq, dev_id);
+ smtc_timer_broadcast(cpu_data[cpu].vpe_id);
+ }
+ }
+#else /* CONFIG_MIPS_MT_SMTC */
+ int r2 = cpu_has_mips_r2;
+