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Merge to Fedora kernel-2.6.18-1.2224_FC5 patched with stable patch-2.6.18.1-vs2.0...
[linux-2.6.git]
/
arch
/
mips
/
mm
/
c-sb1.c
diff --git
a/arch/mips/mm/c-sb1.c
b/arch/mips/mm/c-sb1.c
index
ab30afd
..
2d71efb
100644
(file)
--- a/
arch/mips/mm/c-sb1.c
+++ b/
arch/mips/mm/c-sb1.c
@@
-18,7
+18,6
@@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-#include <linux/config.h>
#include <linux/init.h>
#include <asm/asm.h>
#include <linux/init.h>
#include <asm/asm.h>
@@
-235,7
+234,7
@@
static inline void __sb1_flush_icache_range(unsigned long start,
/*
* Invalidate all caches on this CPU
*/
/*
* Invalidate all caches on this CPU
*/
-static void local_sb1___flush_cache_all(void)
+static void
__attribute_used__
local_sb1___flush_cache_all(void)
{
__sb1_writeback_inv_dcache_all();
__sb1_flush_icache_all();
{
__sb1_writeback_inv_dcache_all();
__sb1_flush_icache_all();
@@
-270,7
+269,7
@@
static void local_sb1_flush_icache_range(unsigned long start,
__sb1_writeback_inv_dcache_all();
else
__sb1_writeback_inv_dcache_range(start, end);
__sb1_writeback_inv_dcache_all();
else
__sb1_writeback_inv_dcache_range(start, end);
-
+
/* Just flush the whole icache if the range is big enough */
if ((end - start) > icache_range_cutoff)
__sb1_flush_icache_all();
/* Just flush the whole icache if the range is big enough */
if ((end - start) > icache_range_cutoff)
__sb1_flush_icache_all();
@@
-492,19
+491,17
@@
static __init void probe_cache_sizes(void)
}
/*
}
/*
- * This is called from
loadmmu
.c. We have to set up all the
+ * This is called from
cache
.c. We have to set up all the
* memory management function pointers, as well as initialize
* the caches and tlbs
*/
* memory management function pointers, as well as initialize
* the caches and tlbs
*/
-void
ld_mmu_sb1
(void)
+void
sb1_cache_init
(void)
{
extern char except_vec2_sb1;
extern char handle_vec2_sb1;
/* Special cache error handler for SB1 */
{
extern char except_vec2_sb1;
extern char handle_vec2_sb1;
/* Special cache error handler for SB1 */
- memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80);
- memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80);
- memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80);
+ set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
probe_cache_sizes();
probe_cache_sizes();
@@
-530,6
+527,7
@@
void ld_mmu_sb1(void)
flush_cache_page = sb1_flush_cache_page;
flush_cache_sigtramp = sb1_flush_cache_sigtramp;
flush_cache_page = sb1_flush_cache_page;
flush_cache_sigtramp = sb1_flush_cache_sigtramp;
+ local_flush_data_cache_page = (void *) sb1_nop;
flush_data_cache_page = (void *) sb1_nop;
/* Full flush */
flush_data_cache_page = (void *) sb1_nop;
/* Full flush */