- if ((config >> 17) & 1)
- return 1;
-
- /*
- * We can't enable the L3 cache yet. There may be board-specific
- * magic necessary to turn it on, and blindly asking the CPU to
- * start using it would may give cache errors.
- *
- * Also, board-specific knowledge may allow us to use the
- * CACHE Flash_Invalidate_T instruction if the tag RAM supports
- * it, and may specify the size of the L3 cache so we don't have
- * to probe it.
- */
- printk(KERN_INFO "Tertiary cache present, %s enabled\n",
- config&(1<<12) ? "already" : "not (yet)");
-
- if ((config >> 12) & 1)
- rm7k_tcache_enabled = 1;
-
- return 1;
-}
-
-struct bcache_ops rm7k_sc_ops = {
- .bc_enable = rm7k_sc_enable,
- .bc_disable = rm7k_sc_disable,
- .bc_wback_inv = rm7k_sc_wback_inv,
- .bc_inv = rm7k_sc_inv
-};
-
-void __init rm7k_sc_init(void)
-{
- if (rm7k_sc_probe()) {
- rm7k_sc_enable();
- bcops = &rm7k_sc_ops;
+ if (!((config >> 17) & 1)) {
+
+ /*
+ * We can't enable the L3 cache yet. There may be board-specific
+ * magic necessary to turn it on, and blindly asking the CPU to
+ * start using it would may give cache errors.
+ *
+ * Also, board-specific knowledge may allow us to use the
+ * CACHE Flash_Invalidate_T instruction if the tag RAM supports
+ * it, and may specify the size of the L3 cache so we don't have
+ * to probe it.
+ */
+ printk(KERN_INFO "Tertiary cache present, %s enabled\n",
+ config&(1<<12) ? "already" : "not (yet)");
+
+ if ((config >> 12) & 1)
+ rm7k_tcache_enabled = 1;