- add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000), 0xfc000000, PM_64K);
- add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000), 0xfc800000, PM_64K);
+ add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
+ 0xfc000000, PM_64K);
+ add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
+ 0xfc800000, PM_64K);
+
+ marvell_base = 0xf4000000;
+}
+
+extern int rm7k_tcache_enabled;
+
+/*
+ * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
+ */
+#define Page_Invalidate_T 0x16
+static void __init setup_l3cache(unsigned long size)
+{
+ int register i;
+
+ printk("Enabling L3 cache...");
+
+ /* Enable the L3 cache in the GT64120A's CPU Configuration register */
+ MV_WRITE(0, MV_READ(0) | (1<<14));
+
+ /* Enable the L3 cache in the CPU */
+ set_c0_config(1<<12 /* CONF_TE */);
+
+ /* Clear the cache */
+ write_c0_taglo(0);
+ write_c0_taghi(0);
+
+ for (i=0; i < size; i+= 4096) {
+ __asm__ __volatile__ (
+ ".set noreorder\n\t"
+ ".set mips3\n\t"
+ "cache %1, (%0)\n\t"
+ ".set mips0\n\t"
+ ".set reorder"
+ :
+ : "r" (KSEG0ADDR(i)),
+ "i" (Page_Invalidate_T));
+ }
+
+ /* Let the RM7000 MM code know that the tertiary cache is enabled */
+ rm7k_tcache_enabled = 1;
+
+ printk("Done\n");
+}