- if (setup->master_memory1 != NULL) {
- master = setup->master_memory1;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIA(master->pci_base_address);
- writel(val, PCIMMAW1REG);
- } else {
- val = readl(PCIMMAW1REG);
- val &= ~WINEN;
- writel(val, PCIMMAW1REG);
- }
-
- if (setup->master_memory2 != NULL) {
- master = setup->master_memory2;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIA(master->pci_base_address);
- writel(val, PCIMMAW2REG);
- } else {
- val = readl(PCIMMAW2REG);
- val &= ~WINEN;
- writel(val, PCIMMAW2REG);
- }
-
- if (setup->target_memory1 != NULL) {
- target = setup->target_memory1;
- val = TARGET_MSK(target->address_mask) |
- WINEN |
- ITA(target->bus_base_address);
- writel(val, PCITAW1REG);
- } else {
- val = readl(PCITAW1REG);
- val &= ~WINEN;
- writel(val, PCITAW1REG);
- }
-
- if (setup->target_memory2 != NULL) {
- target = setup->target_memory2;
- val = TARGET_MSK(target->address_mask) |
- WINEN |
- ITA(target->bus_base_address);
- writel(val, PCITAW2REG);
- } else {
- val = readl(PCITAW2REG);
- val &= ~WINEN;
- writel(val, PCITAW2REG);
- }
-
- if (setup->master_io != NULL) {
- master = setup->master_io;
- val = IBA(master->bus_base_address) |
- MASTER_MSK(master->address_mask) |
- WINEN |
- PCIIA(master->pci_base_address);
- writel(val, PCIMIOAWREG);
- } else {
- val = readl(PCIMIOAWREG);
- val &= ~WINEN;
- writel(val, PCIMIOAWREG);
- }
-
- if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
- writel(UNLOCK, PCIEXACCREG);
- else
- writel(0, PCIEXACCREG);
-
- if (current_cpu_data.cputype == CPU_VR4122)
- writel(TRDYV(setup->wait_time_limit_from_irdy_to_trdy), PCITRDYVREG);
-
- writel(MLTIM(setup->master_latency_timer), LATTIMEREG);
-
- if (setup->mailbox != NULL) {
- mailbox = setup->mailbox;
- val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
- MSI_MEMORY | PREF_APPROVAL;
- writel(val, MAILBAREG);