andi t1, t0, STATUSF_IP2 /* INTB0 hardware line */
bnez t1, ll_pcia_irq /* 64-bit PCI */
andi t1, t0, STATUSF_IP2 /* INTB0 hardware line */
bnez t1, ll_pcia_irq /* 64-bit PCI */
- andi t1, t0, STATUSF_IP3 /* INTB1 hardware line */
- bnez t1, ll_pcib_irq /* second 64-bit PCI slot */
+ andi t2, t0, STATUSF_IP3 /* INTB1 hardware line */
+ bnez t2, ll_pcib_irq /* second 64-bit PCI slot */
andi t1, t0, STATUSF_IP4 /* INTB2 hardware line */
bnez t1, ll_duart_irq /* UART */
andi t1, t0, STATUSF_IP4 /* INTB2 hardware line */
bnez t1, ll_duart_irq /* UART */