+
+/*=======================================================================*/
+
+static int __init vr41xx_icu_init(void)
+{
+ switch (current_cpu_data.cputype) {
+ case CPU_VR4111:
+ case CPU_VR4121:
+ icu1_base = SYSINT1REG_TYPE1;
+ icu2_base = SYSINT2REG_TYPE1;
+ break;
+ case CPU_VR4122:
+ case CPU_VR4131:
+ case CPU_VR4133:
+ icu1_base = SYSINT1REG_TYPE2;
+ icu2_base = SYSINT2REG_TYPE2;
+ break;
+ default:
+ printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n");
+ return -EINVAL;
+ }
+
+ write_icu1(0, MSYSINT1REG);
+ write_icu1(0xffff, MGIUINTLREG);
+
+ write_icu2(0, MSYSINT2REG);
+ write_icu2(0xffff, MGIUINTHREG);
+
+ return 0;
+}
+
+early_initcall(vr41xx_icu_init);
+
+/*=======================================================================*/
+
+static struct irqaction icu_cascade = {no_action, 0, 0, "cascade", NULL, NULL};
+
+static inline void init_vr41xx_icu_irq(void)
+{
+ int i;
+
+ for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
+ irq_desc[i].handler = &sysint1_irq_type;
+
+ for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
+ irq_desc[i].handler = &sysint2_irq_type;
+
+ setup_irq(INT0_CASCADE_IRQ, &icu_cascade);
+ setup_irq(INT1_CASCADE_IRQ, &icu_cascade);
+ setup_irq(INT2_CASCADE_IRQ, &icu_cascade);
+ setup_irq(INT3_CASCADE_IRQ, &icu_cascade);
+ setup_irq(INT4_CASCADE_IRQ, &icu_cascade);
+}
+
+void __init init_IRQ(void)
+{
+ memset(irq_desc, 0, sizeof(irq_desc));
+
+ init_generic_irq();
+ mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
+ init_vr41xx_icu_irq();
+ init_vr41xx_giuint_irq();
+
+ set_except_vector(0, vr41xx_handle_interrupt);
+}