+
+static int __init
+mv64360_register_hdlrs(void)
+{
+ u32 mask;
+ int rc;
+
+ /* Clear old errors and register CPU interface error intr handler */
+ mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
+ if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
+ mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
+ printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
+
+ mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
+ mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
+
+ /* Clear old errors and register internal SRAM error intr handler */
+ mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
+ if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR,
+ mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0)))
+ printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
+
+ /*
+ * Bit 0 reserved on 64360 and erratum FEr PCI-#11 (PCI internal
+ * data parity error set incorrectly) on rev 0 & 1 of 64460 requires
+ * bit 0 to be cleared.
+ */
+ mask = 0x00a50c24;
+
+ if ((mv64x60_get_bridge_type() == MV64x60_TYPE_MV64460) &&
+ (mv64x60_get_bridge_rev() > 1))
+ mask |= 0x1; /* enable DPErr on 64460 */
+
+ /* Clear old errors and register PCI 0 error intr handler */
+ mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
+ if ((rc = request_irq(MV64360_IRQ_PCI0, mv64360_pci_error_int_handler,
+ SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
+ printk(KERN_WARNING "Can't register pci 0 error handler: %d",
+ rc);
+
+ mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
+ mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask);
+
+ /* Clear old errors and register PCI 1 error intr handler */
+ mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
+ if ((rc = request_irq(MV64360_IRQ_PCI1, mv64360_pci_error_int_handler,
+ SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
+ printk(KERN_WARNING "Can't register pci 1 error handler: %d",
+ rc);
+
+ mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, 0);
+ mv64x60_write(&bh, MV64x60_PCI1_ERR_MASK, mask);
+
+ return 0;
+}
+
+arch_initcall(mv64360_register_hdlrs);