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Fedora kernel-2.6.17-1.2142_FC4 patched with stable patch-2.6.17.4-vs2.0.2-rc26.diff
[linux-2.6.git]
/
arch
/
ppc
/
syslib
/
open_pic.c
diff --git
a/arch/ppc/syslib/open_pic.c
b/arch/ppc/syslib/open_pic.c
index
406f36a
..
70456c8
100644
(file)
--- a/
arch/ppc/syslib/open_pic.c
+++ b/
arch/ppc/syslib/open_pic.c
@@
-1,6
+1,4
@@
/*
/*
- * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
- *
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
@@
-13,7
+11,6
@@
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
-#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/errno.h>
@@
-21,10
+18,10
@@
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/prom.h>
#include <asm/sections.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
#include <asm/sections.h>
#include <asm/open_pic.h>
#include <asm/i8259.h>
+#include <asm/machdep.h>
#include "open_pic_defs.h"
#include "open_pic_defs.h"
@@
-78,7
+75,6
@@
static void openpic_mapirq(u_int irq, cpumask_t cpumask, cpumask_t keepmask);
*/
#ifdef notused
static void openpic_enable_8259_pass_through(void);
*/
#ifdef notused
static void openpic_enable_8259_pass_through(void);
-static u_int openpic_get_priority(void);
static u_int openpic_get_spurious(void);
static void openpic_set_sense(u_int irq, int sense);
#endif /* notused */
static u_int openpic_get_spurious(void);
static void openpic_set_sense(u_int irq, int sense);
#endif /* notused */
@@
-220,7
+216,7
@@
static void openpic_safe_writefield(volatile u_int __iomem *addr, u_int mask,
u_int openpic_read_IPI(volatile u_int __iomem * addr)
{
u_int val = 0;
u_int openpic_read_IPI(volatile u_int __iomem * addr)
{
u_int val = 0;
-#if defined(OPENPIC_BIG_ENDIAN)
|| defined(CONFIG_POWER3)
+#if defined(OPENPIC_BIG_ENDIAN)
val = in_be32(addr);
#else
val = in_le32(addr);
val = in_be32(addr);
#else
val = in_le32(addr);
@@
-276,7
+272,7
@@
static void __init openpic_enable_sie(void)
}
#endif
}
#endif
-#if defined(CONFIG_EPIC_SERIAL_MODE)
|| defined(CONFIG_PM)
+#if defined(CONFIG_EPIC_SERIAL_MODE)
static void openpic_reset(void)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
static void openpic_reset(void)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
@@
-372,8
+368,9
@@
void __init openpic_init(int offset)
/* Initialize IPI interrupts */
if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
for (i = 0; i < OPENPIC_NUM_IPI; i++) {
/* Initialize IPI interrupts */
if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
for (i = 0; i < OPENPIC_NUM_IPI; i++) {
- /* Disabled, Priority 10..13 */
- openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
+ /* Disabled, increased priorities 10..13 */
+ openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
+ OPENPIC_VEC_IPI+i+offset);
/* IPIs are per-CPU */
irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
/* IPIs are per-CPU */
irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
@@
-401,8
+398,9
@@
void __init openpic_init(int offset)
if (sense & IRQ_SENSE_MASK)
irq_desc[i+offset].status = IRQ_LEVEL;
if (sense & IRQ_SENSE_MASK)
irq_desc[i+offset].status = IRQ_LEVEL;
- /* Enabled, Priority 8 */
- openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
+ /* Enabled, Default priority */
+ openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
+ (sense & IRQ_POLARITY_MASK),
(sense & IRQ_SENSE_MASK));
/* Processor 0 */
openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
(sense & IRQ_SENSE_MASK));
/* Processor 0 */
openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
@@
-465,8
+463,7
@@
void openpic_eoi(void)
(void)openpic_read(&OpenPIC->THIS_CPU.EOI);
}
(void)openpic_read(&OpenPIC->THIS_CPU.EOI);
}
-#ifdef notused
-static u_int openpic_get_priority(void)
+u_int openpic_get_priority(void)
{
DECL_THIS_CPU;
{
DECL_THIS_CPU;
@@
-474,7
+471,6
@@
static u_int openpic_get_priority(void)
return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
OPENPIC_CURRENT_TASK_PRIORITY_MASK);
}
return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
OPENPIC_CURRENT_TASK_PRIORITY_MASK);
}
-#endif /* notused */
void openpic_set_priority(u_int pri)
{
void openpic_set_priority(u_int pri)
{
@@
-560,12
+556,10
@@
static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
*/
void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
{
*/
void openpic_cause_IPI(u_int ipi, cpumask_t cpumask)
{
- cpumask_t phys;
DECL_THIS_CPU;
CHECK_THIS_CPU;
check_arg_ipi(ipi);
DECL_THIS_CPU;
CHECK_THIS_CPU;
check_arg_ipi(ipi);
- phys = physmask(cpumask);
openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
cpus_addr(physmask(cpumask))[0]);
}
openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
cpus_addr(physmask(cpumask))[0]);
}
@@
-661,6
+655,18
@@
static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
cpus_addr(phys)[0]);
}
cpus_addr(phys)[0]);
}
+/*
+ * Change the priority of an interrupt
+ */
+void __init
+openpic_set_irq_priority(u_int irq, u_int pri)
+{
+ check_arg_irq(irq);
+ openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
+ OPENPIC_PRIORITY_MASK,
+ pri << OPENPIC_PRIORITY_SHIFT);
+}
+
/*
* Initalize the interrupt source which will generate an NMI.
* This raises the interrupt's priority from 8 to 9.
/*
* Initalize the interrupt source which will generate an NMI.
* This raises the interrupt's priority from 8 to 9.
@@
-671,9
+677,7
@@
void __init
openpic_init_nmi_irq(u_int irq)
{
check_arg_irq(irq);
openpic_init_nmi_irq(u_int irq)
{
check_arg_irq(irq);
- openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
- OPENPIC_PRIORITY_MASK,
- 9 << OPENPIC_PRIORITY_SHIFT);
+ openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
}
/*
}
/*
@@
-884,7
+888,7
@@
openpic_get_irq(struct pt_regs *regs)
#ifdef CONFIG_SMP
void
#ifdef CONFIG_SMP
void
-smp_openpic_message_pass(int target, int msg
, unsigned long data, int wait
)
+smp_openpic_message_pass(int target, int msg)
{
cpumask_t mask = CPU_MASK_ALL;
/* make sure we're sending something that translates to an IPI */
{
cpumask_t mask = CPU_MASK_ALL;
/* make sure we're sending something that translates to an IPI */
@@
-942,7
+946,7
@@
static void openpic_cached_disable_irq(u_int irq)
* we need something better to deal with that... Maybe switch to S1 for
* cpufreq changes
*/
* we need something better to deal with that... Maybe switch to S1 for
* cpufreq changes
*/
-int openpic_suspend(struct sys_device *sysdev,
u32
state)
+int openpic_suspend(struct sys_device *sysdev,
pm_message_t
state)
{
int i;
unsigned long flags;
{
int i;
unsigned long flags;
@@
-998,8
+1002,6
@@
int openpic_resume(struct sys_device *sysdev)
return 0;
}
return 0;
}
- openpic_reset();
-
/* OpenPIC sometimes seem to need some time to be fully back up... */
do {
openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
/* OpenPIC sometimes seem to need some time to be fully back up... */
do {
openpic_set_spurious(OPENPIC_VEC_SPURIOUS);