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vserver 1.9.5.x5
[linux-2.6.git]
/
arch
/
ppc64
/
mm
/
slb.c
diff --git
a/arch/ppc64/mm/slb.c
b/arch/ppc64/mm/slb.c
index
7424d8d
..
12493ca
100644
(file)
--- a/
arch/ppc64/mm/slb.c
+++ b/
arch/ppc64/mm/slb.c
@@
-19,7
+19,6
@@
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/paca.h>
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/paca.h>
-#include <asm/naca.h>
#include <asm/cputable.h>
extern void slb_allocate(unsigned long ea);
#include <asm/cputable.h>
extern void slb_allocate(unsigned long ea);
@@
-79,7
+78,7
@@
static void slb_flush_and_rebolt(void)
void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
{
unsigned long offset = get_paca()->slb_cache_ptr;
void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
{
unsigned long offset = get_paca()->slb_cache_ptr;
- unsigned long esid_data;
+ unsigned long esid_data
= 0
;
unsigned long pc = KSTK_EIP(tsk);
unsigned long stack = KSTK_ESP(tsk);
unsigned long unmapped_base;
unsigned long pc = KSTK_EIP(tsk);
unsigned long stack = KSTK_ESP(tsk);
unsigned long unmapped_base;
@@
-98,11
+97,8
@@
void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
}
/* Workaround POWER5 < DD2.1 issue */
}
/* Workaround POWER5 < DD2.1 issue */
- if (offset == 1 || offset > SLB_CACHE_ENTRIES) {
- /* flush segment in EEH region, we shouldn't ever
- * access addresses in this region. */
- asm volatile("slbie %0" : : "r"(EEHREGIONBASE));
- }
+ if (offset == 1 || offset > SLB_CACHE_ENTRIES)
+ asm volatile("slbie %0" : : "r" (esid_data));
get_paca()->slb_cache_ptr = 0;
get_paca()->context = mm->context;
get_paca()->slb_cache_ptr = 0;
get_paca()->context = mm->context;