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fedora core 6 1.2949 + vserver 2.2.0
[linux-2.6.git]
/
arch
/
s390
/
math-emu
/
math.c
diff --git
a/arch/s390/math-emu/math.c
b/arch/s390/math-emu/math.c
index
648df71
..
6b9aec5
100644
(file)
--- a/
arch/s390/math-emu/math.c
+++ b/
arch/s390/math-emu/math.c
@@
-9,7
+9,6
@@
* that does not have the IEEE fpu (all processors before G5).
*/
* that does not have the IEEE fpu (all processors before G5).
*/
-#include <linux/config.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/mm.h>
@@
-1565,52
+1564,52
@@
static int emu_tceb (struct pt_regs *regs, int rx, long val) {
}
static inline void emu_load_regd(int reg) {
}
static inline void emu_load_regd(int reg) {
-
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
+
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
return;
return;
-
asm volatile (
/* load reg from fp_regs.fprs[reg] */
-
" bras
1,0f\n"
-
" ld
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" (reg<<4),"a" (¤t->thread.fp_regs.fprs[reg].d)
-
: "1"
);
+
asm volatile(
/* load reg from fp_regs.fprs[reg] */
+
" bras
1,0f\n"
+
" ld
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" (reg<<4),"a" (¤t->thread.fp_regs.fprs[reg].d)
+
: "1"
);
}
static inline void emu_load_rege(int reg) {
}
static inline void emu_load_rege(int reg) {
-
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
+
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
return;
return;
-
asm volatile (
/* load reg from fp_regs.fprs[reg] */
-
" bras
1,0f\n"
-
" le
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].f)
-
: "1"
);
+
asm volatile(
/* load reg from fp_regs.fprs[reg] */
+
" bras
1,0f\n"
+
" le
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].f)
+
: "1"
);
}
static inline void emu_store_regd(int reg) {
}
static inline void emu_store_regd(int reg) {
-
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
+
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
return;
return;
-
asm volatile (
/* store reg to fp_regs.fprs[reg] */
-
" bras
1,0f\n"
-
" std
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].d)
-
: "1"
);
+
asm volatile(
/* store reg to fp_regs.fprs[reg] */
+
" bras
1,0f\n"
+
" std
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].d)
+
: "1"
);
}
static inline void emu_store_rege(int reg) {
}
static inline void emu_store_rege(int reg) {
-
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
+
if ((reg&9) != 0)
/* test if reg in {0,2,4,6} */
return;
return;
-
asm volatile (
/* store reg to fp_regs.fprs[reg] */
-
" bras
1,0f\n"
-
" ste
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].f)
-
: "1"
);
+
asm volatile(
/* store reg to fp_regs.fprs[reg] */
+
" bras
1,0f\n"
+
" ste
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" (reg<<4), "a" (¤t->thread.fp_regs.fprs[reg].f)
+
: "1"
);
}
int math_emu_b3(__u8 *opcode, struct pt_regs * regs) {
}
int math_emu_b3(__u8 *opcode, struct pt_regs * regs) {
@@
-2090,23
+2089,22
@@
int math_emu_ldr(__u8 *opcode) {
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
- __asm__ __volatile ( /* load rx from fp_regs.fprs[ry] */
- " bras 1,0f\n"
- " ld 0,0(%1)\n"
- "0: ex %0,0(1)"
- : /* no output */
- : "a" (opc & 0xf0),
- "a" (&fp_regs->fprs[opc & 0xf].d)
- : "1" );
+ asm volatile( /* load rx from fp_regs.fprs[ry] */
+ " bras 1,0f\n"
+ " ld 0,0(%1)\n"
+ "0: ex %0,0(1)"
+ : /* no output */
+ : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].d)
+ : "1");
} else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
} else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
-
__asm__ __volatile (
/* store ry to fp_regs.fprs[rx] */
-
" bras
1,0f\n"
-
" std
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" ((opc & 0xf) << 4),
-
"a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
-
: "1"
);
+
asm volatile (
/* store ry to fp_regs.fprs[rx] */
+
" bras
1,0f\n"
+
" std
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" ((opc & 0xf) << 4),
+ "a" (&fp_regs->fprs[(opc & 0xf0)>>4].d)
+
: "1"
);
} else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
return 0;
} else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
return 0;
@@
-2121,23
+2119,22
@@
int math_emu_ler(__u8 *opcode) {
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
if ((opc & 0x90) == 0) { /* test if rx in {0,2,4,6} */
/* we got an exception therfore ry can't be in {0,2,4,6} */
- __asm__ __volatile ( /* load rx from fp_regs.fprs[ry] */
- " bras 1,0f\n"
- " le 0,0(%1)\n"
- "0: ex %0,0(1)"
- : /* no output */
- : "a" (opc & 0xf0),
- "a" (&fp_regs->fprs[opc & 0xf].f)
- : "1" );
+ asm volatile( /* load rx from fp_regs.fprs[ry] */
+ " bras 1,0f\n"
+ " le 0,0(%1)\n"
+ "0: ex %0,0(1)"
+ : /* no output */
+ : "a" (opc & 0xf0), "a" (&fp_regs->fprs[opc & 0xf].f)
+ : "1");
} else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
} else if ((opc & 0x9) == 0) { /* test if ry in {0,2,4,6} */
-
__asm__ __volatile (
/* store ry to fp_regs.fprs[rx] */
-
" bras
1,0f\n"
-
" ste
0,0(%1)\n"
-
"0: ex
%0,0(1)"
-
: /* no output */
-
: "a" ((opc & 0xf) << 4),
-
"a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
-
: "1"
);
+
asm volatile(
/* store ry to fp_regs.fprs[rx] */
+
" bras
1,0f\n"
+
" ste
0,0(%1)\n"
+
"0: ex
%0,0(1)"
+ : /* no output */
+ : "a" ((opc & 0xf) << 4),
+ "a" (&fp_regs->fprs[(opc & 0xf0) >> 4].f)
+
: "1"
);
} else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
return 0;
} else /* move fp_regs.fprs[ry] to fp_regs.fprs[rx] */
fp_regs->fprs[(opc & 0xf0) >> 4] = fp_regs->fprs[opc & 0xf];
return 0;