-int __init detect_cpu_and_cache_system(void)
-{
- unsigned long pvr, prr, ccr, cvr;
- unsigned long size;
-
- static unsigned long sizes[16] = {
- [1] = (1 << 12),
- [2] = (1 << 13),
- [4] = (1 << 14),
- [8] = (1 << 15),
- [9] = (1 << 16)
- };
-
- pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
- prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
- cvr = (ctrl_inl(CCN_CVR));
-
- /*
- * Setup some sane SH-4 defaults for the icache
- */
- cpu_data->icache.way_shift = 13;
- cpu_data->icache.entry_shift = 5;
- cpu_data->icache.entry_mask = 0x1fe0;
- cpu_data->icache.sets = 256;
- cpu_data->icache.ways = 1;
- cpu_data->icache.linesz = L1_CACHE_BYTES;
-
- /*
- * And again for the dcache ..
- */
- cpu_data->dcache.way_shift = 14;
- cpu_data->dcache.entry_shift = 5;
- cpu_data->dcache.entry_mask = 0x3fe0;
- cpu_data->dcache.sets = 512;
- cpu_data->dcache.ways = 1;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
-
- /* Set the FPU flag, virtually all SH-4's have one */
- set_bit(CPU_HAS_FPU, &(cpu_data->flags));
-
- /*
- * Probe the underlying processor version/revision and
- * adjust cpu_data setup accordingly.
- */
- switch (pvr) {
- case 0x205:
- cpu_data->type = CPU_SH7750;
- set_bit(CPU_HAS_P2_FLUSH_BUG, &(cpu_data->flags));
- break;
- case 0x206:
- cpu_data->type = CPU_SH7750S;
-
- /*
- * FIXME: This is needed for 7750, but do we need it for the
- * 7750S too? For now, assume we do.. -- PFM
- */
- set_bit(CPU_HAS_P2_FLUSH_BUG, &(cpu_data->flags));
-
- break;
- case 0x1100:
- cpu_data->type = CPU_SH7751;
- break;
- case 0x8000:
- cpu_data->type = CPU_ST40RA;
- break;
- case 0x8100:
- cpu_data->type = CPU_ST40GX1;
- break;
- case 0x700:
- cpu_data->type = CPU_SH4_501;
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
-
- /* No FPU on the SH4-500 series.. */
- clear_bit(CPU_HAS_FPU, &(cpu_data->flags));
- break;
- case 0x600:
- cpu_data->type = CPU_SH4_202;
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
- break;
- case 0x500 ... 0x501:
- switch (prr) {
- case 0x10: cpu_data->type = CPU_SH7750R; break;
- case 0x11: cpu_data->type = CPU_SH7751R; break;
- case 0x50: cpu_data->type = CPU_SH7760; break;
- }
-
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
-
- break;
- default:
- cpu_data->type = CPU_SH_NONE;
- break;
- }
-
- /*
- * On anything that's not a direct-mapped cache, look to the CVR
- * for I/D-cache specifics.
- */
- if (cpu_data->dcache.ways > 1) {
- jump_to_P2();
- ccr = ctrl_inl(CCR);
-
- /* Force EMODE */
- if (!(ccr & CCR_CACHE_EMODE)) {
- ccr |= CCR_CACHE_EMODE;
- ctrl_outl(ccr, CCR);
- }
-
- back_to_P1();
-
- size = sizes[(cvr >> 20) & 0xf];
- cpu_data->icache.way_shift = (size >> 1);
- cpu_data->icache.entry_mask = ((size >> 2) - (1 << 5));
- cpu_data->icache.sets = (size >> 6);
-
- size = sizes[(cvr >> 16) & 0xf];
- cpu_data->dcache.way_shift = (size >> 1);
- cpu_data->dcache.entry_mask = ((size >> 2) - (1 << 5));
- cpu_data->dcache.sets = (size >> 6);
- }
-
- return 0;
-}
-