-static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
-{
- unsigned int bus = (ino & 0x10) >> 4;
- unsigned int slot = (ino & 0x0c) >> 2;
-
- if (bus == 0)
- return SABRE_IMAP_A_SLOT0 + (slot * 8);
- else
- return SABRE_IMAP_B_SLOT0 + (slot * 8);
-}
-
-static unsigned long __onboard_imap_off[] = {
-/*0x20*/ SABRE_IMAP_SCSI,
-/*0x21*/ SABRE_IMAP_ETH,
-/*0x22*/ SABRE_IMAP_BPP,
-/*0x23*/ SABRE_IMAP_AU_REC,
-/*0x24*/ SABRE_IMAP_AU_PLAY,
-/*0x25*/ SABRE_IMAP_PFAIL,
-/*0x26*/ SABRE_IMAP_KMS,
-/*0x27*/ SABRE_IMAP_FLPY,
-/*0x28*/ SABRE_IMAP_SHW,
-/*0x29*/ SABRE_IMAP_KBD,
-/*0x2a*/ SABRE_IMAP_MS,
-/*0x2b*/ SABRE_IMAP_SER,
-/*0x2c*/ 0 /* reserved */,
-/*0x2d*/ 0 /* reserved */,
-/*0x2e*/ SABRE_IMAP_UE,
-/*0x2f*/ SABRE_IMAP_CE,
-/*0x30*/ SABRE_IMAP_PCIERR,
-};
-#define SABRE_ONBOARD_IRQ_BASE 0x20
-#define SABRE_ONBOARD_IRQ_LAST 0x30
-#define sabre_onboard_imap_offset(__ino) \
- __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
-
-#define sabre_iclr_offset(ino) \
- ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
- (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
-
-/* PCI SABRE INO number to Sparc PIL level. */
-static unsigned char sabre_pil_table[] = {
-/*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
-/*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
-/*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
-/*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
-/*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
-/*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
-/*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
-/*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
-/*0x20*/5, /* SCSI */
-/*0x21*/5, /* Ethernet */
-/*0x22*/8, /* Parallel Port */
-/*0x23*/13, /* Audio Record */
-/*0x24*/14, /* Audio Playback */
-/*0x25*/15, /* PowerFail */
-/*0x26*/5, /* second SCSI */
-/*0x27*/11, /* Floppy */
-/*0x28*/5, /* Spare Hardware */
-/*0x29*/9, /* Keyboard */
-/*0x2a*/5, /* Mouse */
-/*0x2b*/12, /* Serial */
-/*0x2c*/10, /* Timer 0 */
-/*0x2d*/11, /* Timer 1 */
-/*0x2e*/15, /* Uncorrectable ECC */
-/*0x2f*/15, /* Correctable ECC */
-/*0x30*/15, /* PCI Bus A Error */
-/*0x31*/15, /* PCI Bus B Error */
-/*0x32*/15, /* Power Management */
-};
-
-static int sabre_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
-{
- int ret;
-
- if (pdev &&
- pdev->vendor == PCI_VENDOR_ID_SUN &&
- pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
- return 9;
-
- ret = sabre_pil_table[ino];
- if (ret == 0 && pdev == NULL) {
- ret = 5;
- } else if (ret == 0) {
- switch ((pdev->class >> 16) & 0xff) {
- case PCI_BASE_CLASS_STORAGE:
- ret = 5;
- break;
-
- case PCI_BASE_CLASS_NETWORK:
- ret = 6;
- break;
-
- case PCI_BASE_CLASS_DISPLAY:
- ret = 9;
- break;
-
- case PCI_BASE_CLASS_MULTIMEDIA:
- case PCI_BASE_CLASS_MEMORY:
- case PCI_BASE_CLASS_BRIDGE:
- case PCI_BASE_CLASS_SERIAL:
- ret = 10;
- break;
-
- default:
- ret = 5;
- break;
- };
- }
- return ret;
-}
-
-/* When a device lives behind a bridge deeper in the PCI bus topology
- * than APB, a special sequence must run to make sure all pending DMA
- * transfers at the time of IRQ delivery are visible in the coherency
- * domain by the cpu. This sequence is to perform a read on the far
- * side of the non-APB bridge, then perform a read of Sabre's DMA
- * write-sync register.
- */
-static void sabre_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
-{
- struct pci_dev *pdev = _arg1;
- unsigned long sync_reg = (unsigned long) _arg2;
- u16 _unused;
-
- pci_read_config_word(pdev, PCI_VENDOR_ID, &_unused);
- sabre_read(sync_reg);
-}
-
-static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
- struct pci_dev *pdev,
- unsigned int ino)
-{
- struct ino_bucket *bucket;
- unsigned long imap, iclr;
- unsigned long imap_off, iclr_off;
- int pil, inofixup = 0;
-
- ino &= PCI_IRQ_INO;
- if (ino < SABRE_ONBOARD_IRQ_BASE) {
- /* PCI slot */
- imap_off = sabre_pcislot_imap_offset(ino);
- } else {
- /* onboard device */
- if (ino > SABRE_ONBOARD_IRQ_LAST) {
- prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
- prom_halt();
- }
- imap_off = sabre_onboard_imap_offset(ino);
- }
-
- /* Now build the IRQ bucket. */
- pil = sabre_ino_to_pil(pdev, ino);
-
- if (PIL_RESERVED(pil))
- BUG();
-
- imap = pbm->controller_regs + imap_off;
- imap += 4;
-
- iclr_off = sabre_iclr_offset(ino);
- iclr = pbm->controller_regs + iclr_off;
- iclr += 4;
-
- if ((ino & 0x20) == 0)
- inofixup = ino & 0x03;
-
- bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
- bucket->flags |= IBF_PCI;
-
- if (pdev) {
- struct pcidev_cookie *pcp = pdev->sysdata;
-
- if (pdev->bus->number != pcp->pbm->pci_first_busno) {
- struct pci_controller_info *p = pcp->pbm->parent;
- struct irq_desc *d = bucket->irq_info;
-
- d->pre_handler = sabre_wsync_handler;
- d->pre_handler_arg1 = pdev;
- d->pre_handler_arg2 = (void *)
- p->pbm_A.controller_regs + SABRE_WRSYNC;
- }
- }
- return __irq(bucket);
-}
-