-#define SYSIO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
-#define SYSIO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
-#define SYSIO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
-#define SYSIO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
-#define SYSIO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
-#define SYSIO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
-#define SYSIO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */
-#define SYSIO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */
-#define SYSIO_CEAFSR_DOFF 0x0000e00000000000 /* Double Offset */
-#define SYSIO_CEAFSR_SIZE 0x00001c0000000000 /* Bad transfer size is 2**SIZE */
-#define SYSIO_CEAFSR_MID 0x000003e000000000 /* UPA MID causing the fault */
-#define SYSIO_CEAFSR_RESV2 0x0000001fffffffff /* Reserved */
+#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
+#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
+#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
+#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
+#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
+#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
+#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
+#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
+#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
+#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
+#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
+#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */