-
-
-/* Bit fields for particular registers */
-
-/* GCR */
-#define GCR_SERIAL 0x00 /* Configure as serial channel */
-#define GCR_PARALLEL 0x80 /* Configure as parallel channel */
-
-/* RDSR - when status read from FIFO */
-#define RDSR_BREAK 0x08 /* Break received */
-#define RDSR_TIMEOUT 0x80 /* No new data timeout */
-#define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */
-#define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */
-#define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */
-
-/* PPR */
-#define PPR_DEFAULT 0x31 /* Default value - for a 25Mhz clock gives
- a timeout period of 1ms */
-
-/* LIVR */
-#define LIVR_EXCEPTION 0x07 /* Receive exception interrupt */
-
-/* CCR */
-#define CCR_RESET 0x80 /* Reset channel */
-#define CCR_CHANGE 0x4e /* COR's have changed - NB always change all
- COR's */
-#define CCR_WFLUSH 0x82 /* Flush transmit FIFO and TSR / THR */
-
-#define CCR_SENDSC1 0x21 /* Send special character one */
-#define CCR_SENDSC2 0x22 /* Send special character two */
-#define CCR_SENDSC3 0x23 /* Send special character three */
-#define CCR_SENDSC4 0x24 /* Send special character four */
-
-#define CCR_TENABLE 0x18 /* Enable transmitter */
-#define CCR_TDISABLE 0x14 /* Disable transmitter */
-#define CCR_RENABLE 0x12 /* Enable receiver */
-#define CCR_RDISABLE 0x11 /* Disable receiver */
-
-#define CCR_READY 0x00 /* CCR is ready for another command */
-
-/* CCSR */
-#define CCSR_TXENABLE 0x08 /* Transmitter enable */
-#define CCSR_RXENABLE 0x80 /* Receiver enable */
-#define CCSR_TXFLOWOFF 0x04 /* Transmit flow off */
-#define CCSR_TXFLOWON 0x02 /* Transmit flow on */
-
-/* SVRR */
-#define SVRR_RECEIVE 0x01 /* Receive interrupt pending */
-#define SVRR_TRANSMIT 0x02 /* Transmit interrupt pending */
-#define SVRR_MODEM 0x04 /* Modem interrupt pending */
-
-/* CAR */
-#define CAR_PORTS 0x03 /* Bit fields for ports */
-
-/* IER */
-#define IER_MODEM 0x80 /* Change in modem status */
-#define IER_RECEIVE 0x10 /* Good data / data exception */
-#define IER_TRANSMITR 0x04 /* Transmit ready (FIFO empty) */
-#define IER_TRANSMITE 0x02 /* Transmit empty */
-#define IER_TIMEOUT 0x01 /* Timeout on no data */
-
-#define IER_DEFAULT 0x94 /* Default values */
-#define IER_PARALLEL 0x84 /* Default for Parallel */
-#define IER_EMPTY 0x92 /* Transmitter empty rather than ready */
-
-/* COR1 - Driver only */
-#define COR1_INPCK 0x10 /* Check parity of received characters */