-static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
-{
- unsigned long last_cumul_size;
- u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
- u16 value;
- u32 cumul_size;
- struct csrow_info *csrow;
- int index;
-
- pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
- mchcfg_ddim = mchcfg_ddim & 0x180;
- last_cumul_size = 0;
-
- /* The group row boundary (GRA) reg values are boundary address
- * for each DRAM row with a granularity of 16MB. GRA regs are
- * cumulative; therefore GRA15 will contain the total memory contained
- * in all eight rows.
- */
- for (index = 0; index < mci->nr_csrows; index++) {
- csrow = &mci->csrows[index];
- pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
- cumul_size = (value & I82860_GBA_MASK) <<
- (I82860_GBA_SHIFT - PAGE_SHIFT);
- debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
- cumul_size);
-
- if (cumul_size == last_cumul_size)
- continue; /* not populated */
-
- csrow->first_page = last_cumul_size;
- csrow->last_page = cumul_size - 1;
- csrow->nr_pages = cumul_size - last_cumul_size;
- last_cumul_size = cumul_size;
- csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
- csrow->mtype = MEM_RMBS;
- csrow->dtype = DEV_UNKNOWN;
- csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
- }
-}
-