- /* upload brs */
- WRITE_RPS1(CMD_UPLOAD | MASK_08);
- /* load brs-control register */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
- /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
- WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
- /* wait for brs_done */
- WRITE_RPS1(CMD_PAUSE | MASK_08);
- /* upload brs */
- WRITE_RPS1(CMD_UPLOAD | MASK_08);
- /* load video-dma3 NumLines3 and NumBytes3 */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
- /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
- WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
- /* load brs-control register */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
- /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
- WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
- /* wait for brs_done */
- WRITE_RPS1(CMD_PAUSE | MASK_08);
- /* upload brs and video-dma3*/
- WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
- /* load mc2 register: enable dma3 */
- WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
- WRITE_RPS1(MASK_20 | MASK_04);
- /* generate interrupt */
- WRITE_RPS1(CMD_INTERRUPT);
- /* stop rps1 */
- WRITE_RPS1(CMD_STOP);
-
+ /* upload brs */
+ WRITE_RPS1(CMD_UPLOAD | MASK_08);
+ /* load brs-control register */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
+ /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
+ WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
+ /* wait for brs_done */
+ WRITE_RPS1(CMD_PAUSE | MASK_08);
+ /* upload brs */
+ WRITE_RPS1(CMD_UPLOAD | MASK_08);
+ /* load video-dma3 NumLines3 and NumBytes3 */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
+ /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
+ WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
+ /* load brs-control register */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
+ /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
+ WRITE_RPS1((540 << 7) | (5 << 19)); // 5 == vbi_start
+ /* wait for brs_done */
+ WRITE_RPS1(CMD_PAUSE | MASK_08);
+ /* upload brs and video-dma3*/
+ WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
+ /* load mc2 register: enable dma3 */
+ WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
+ WRITE_RPS1(MASK_20 | MASK_04);
+ /* generate interrupt */
+ WRITE_RPS1(CMD_INTERRUPT);
+ /* stop rps1 */
+ WRITE_RPS1(CMD_STOP);
+