- wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
-
- wr(DIB3000MB_REG_UNK_68,DIB3000MB_UNK_68);
- wr(DIB3000MB_REG_UNK_69,DIB3000MB_UNK_69);
- wr(DIB3000MB_REG_UNK_71,DIB3000MB_UNK_71);
- wr(DIB3000MB_REG_UNK_77,DIB3000MB_UNK_77);
- wr(DIB3000MB_REG_UNK_78,DIB3000MB_UNK_78);
- wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
- wr(DIB3000MB_REG_UNK_92,DIB3000MB_UNK_92);
- wr(DIB3000MB_REG_UNK_96,DIB3000MB_UNK_96);
- wr(DIB3000MB_REG_UNK_97,DIB3000MB_UNK_97);
- wr(DIB3000MB_REG_UNK_106,DIB3000MB_UNK_106);
- wr(DIB3000MB_REG_UNK_107,DIB3000MB_UNK_107);
- wr(DIB3000MB_REG_UNK_108,DIB3000MB_UNK_108);
- wr(DIB3000MB_REG_UNK_122,DIB3000MB_UNK_122);
- wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
- wr(DIB3000MB_REG_BERLEN,DIB3000MB_BERLEN_DEFAULT);
-
- wr_foreach(dib3000mb_reg_filter_coeffs,dib3000mb_filter_coeffs);
-
- wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_ON);
- wr(DIB3000MB_REG_MULTI_DEMOD_MSB,DIB3000MB_MULTI_DEMOD_MSB);
- wr(DIB3000MB_REG_MULTI_DEMOD_LSB,DIB3000MB_MULTI_DEMOD_LSB);
-
- wr(DIB3000MB_REG_OUTPUT_MODE,DIB3000MB_OUTPUT_MODE_SLAVE);
-
- wr(DIB3000MB_REG_FIFO_142,DIB3000MB_FIFO_142);
- wr(DIB3000MB_REG_MPEG2_OUT_MODE,DIB3000MB_MPEG2_OUT_MODE_188);
+ wr_foreach(dib3000mb_reg_bandwidth, dib3000mb_bandwidth_8mhz);
+
+ wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);
+ wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);
+ wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);
+ wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);
+ wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);
+ wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);
+ wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);
+ wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);
+ wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);
+ wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);
+ wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);
+ wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);
+ wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);
+ wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);
+ wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);
+
+ wr_foreach(dib3000mb_reg_filter_coeffs, dib3000mb_filter_coeffs);
+
+ wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);
+ wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);
+ wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);
+
+ wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);
+
+ wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);
+ wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);