+static int pll_write (struct dvb_i2c_bus *i2c, u8 addr, u8 *data, int len)
+{
+ int ret;
+ struct i2c_msg msg = { .addr = addr, .buf = data, .len = len };
+
+
+ stv0299_writereg(i2c, 0x05, 0xb5); /* enable i2c repeater on stv0299 */
+
+ ret = i2c->xfer (i2c, &msg, 1);
+
+ stv0299_writereg(i2c, 0x05, 0x35); /* disable i2c repeater on stv0299 */
+
+ if (ret != 1)
+ dprintk("%s: i/o error (ret == %i)\n", __FUNCTION__, ret);
+
+ return (ret != 1) ? -1 : 0;
+}
+
+
+static int sl1935_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq, int ftype)
+{
+ u8 buf[4];
+ u32 div;
+
+ div = freq / 125;
+
+ dprintk("%s : freq = %i, div = %i\n", __FUNCTION__, freq, div);
+
+ buf[0] = (div >> 8) & 0x7f;
+ buf[1] = div & 0xff;
+ buf[2] = 0x84; // 0xC4
+ buf[3] = 0x08;
+
+ if (freq < 1500000) buf[3] |= 0x10;
+
+ return pll_write (i2c, 0x61, buf, sizeof(buf));
+}
+
+/**
+ * set up the downconverter frequency divisor for a
+ * reference clock comparision frequency of 125 kHz.
+ */
+static int tsa5059_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq, int ftype, int srate)
+{
+ u8 addr;
+ u32 div;
+ u8 buf[4];
+ int divisor, regcode;
+
+ dprintk ("%s: freq %i, ftype %i\n", __FUNCTION__, freq, ftype);
+
+ if ((freq < 950000) || (freq > 2150000)) return -EINVAL;
+
+ if (ftype == PHILIPS_SU1278_TSA_TT) {
+ divisor = 500;
+ regcode = 2;
+ } else {
+ divisor = 125;
+ regcode = 4;
+ }
+
+ // setup frequency divisor
+ div = (freq + (divisor - 1)) / divisor; // round correctly
+ buf[0] = (div >> 8) & 0x7f;
+ buf[1] = div & 0xff;
+ buf[2] = 0x80 | ((div & 0x18000) >> 10) | regcode;
+ buf[3] = 0;
+
+ // tuner-specific settings
+ switch(ftype) {
+ case PHILIPS_SU1278_TSA:
+ case PHILIPS_SU1278_TSA_TT:
+ case PHILIPS_SU1278_TSA_TY:
+ if (ftype == PHILIPS_SU1278_TSA_TY)
+ addr = 0x61;
+ else
+ addr = 0x60;
+
+ buf[3] |= 0x20;
+
+ if (srate < 4000000) buf[3] |= 1;
+
+ if (freq < 1250000) buf[3] |= 0;
+ else if (freq < 1550000) buf[3] |= 0x40;
+ else if (freq < 2050000) buf[3] |= 0x80;
+ else if (freq < 2150000) buf[3] |= 0xC0;
+ break;
+
+ case ALPS_BSRU6:
+ addr = 0x61;
+ buf[3] = 0xC4;
+ if (freq > 1530000) buf[3] = 0xc0;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ return pll_write (i2c, addr, buf, sizeof(buf));
+}
+
+
+#define MIN2(a,b) ((a) < (b) ? (a) : (b))
+#define MIN3(a,b,c) MIN2(MIN2(a,b),c)
+
+static int tua6100_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq,
+ int ftype, int srate)
+{
+ u8 reg0 [2] = { 0x00, 0x00 };
+ u8 reg1 [4] = { 0x01, 0x00, 0x00, 0x00 };
+ u8 reg2 [3] = { 0x02, 0x00, 0x00 };
+ int _fband;
+ int first_ZF;
+ int R, A, N, P, M;
+ int err;
+
+ first_ZF = (freq) / 1000;
+
+ if (abs(MIN2(abs(first_ZF-1190),abs(first_ZF-1790))) <
+ abs(MIN3(abs(first_ZF-1202),abs(first_ZF-1542),abs(first_ZF-1890))))
+ _fband = 2;
+ else
+ _fband = 3;
+
+ if (_fband == 2) {
+ if (((first_ZF >= 950) && (first_ZF < 1350)) ||
+ ((first_ZF >= 1430) && (first_ZF < 1950)))
+ reg0[1] = 0x07;
+ else if (((first_ZF >= 1350) && (first_ZF < 1430)) ||
+ ((first_ZF >= 1950) && (first_ZF < 2150)))
+ reg0[1] = 0x0B;
+ }
+
+ if(_fband == 3) {
+ if (((first_ZF >= 950) && (first_ZF < 1350)) ||
+ ((first_ZF >= 1455) && (first_ZF < 1950)))
+ reg0[1] = 0x07;
+ else if (((first_ZF >= 1350) && (first_ZF < 1420)) ||
+ ((first_ZF >= 1950) && (first_ZF < 2150)))
+ reg0[1] = 0x0B;
+ else if ((first_ZF >= 1420) && (first_ZF < 1455))
+ reg0[1] = 0x0F;
+}
+
+ if (first_ZF > 1525)
+ reg1[1] |= 0x80;
+ else
+ reg1[1] &= 0x7F;
+
+ if (_fband == 2) {
+ if (first_ZF > 1430) { /* 1430MHZ */
+ reg1[1] &= 0xCF; /* N2 */
+ reg2[1] &= 0xCF; /* R2 */
+ reg2[1] |= 0x10;
+ } else {
+ reg1[1] &= 0xCF; /* N2 */
+ reg1[1] |= 0x20;
+ reg2[1] &= 0xCF; /* R2 */
+ reg2[1] |= 0x10;
+ }
+}
+
+ if (_fband == 3) {
+ if ((first_ZF >= 1455) &&
+ (first_ZF < 1630)) {
+ reg1[1] &= 0xCF; /* N2 */
+ reg1[1] |= 0x20;
+ reg2[1] &= 0xCF; /* R2 */
+ } else {
+ if (first_ZF < 1455) {
+ reg1[1] &= 0xCF; /* N2 */
+ reg1[1] |= 0x20;
+ reg2[1] &= 0xCF; /* R2 */
+ reg2[1] |= 0x10;
+ } else {
+ if (first_ZF >= 1630) {
+ reg1[1] &= 0xCF; /* N2 */
+ reg2[1] &= 0xCF; /* R2 */
+ reg2[1] |= 0x10;
+ }
+ }
+ }
+ }
+
+ /* set ports, enable P0 for symbol rates > 4Ms/s */
+ if (srate >= 4000000)
+ reg1[1] |= 0x0c;
+ else
+ reg1[1] |= 0x04;
+
+ reg2[1] |= 0x0c;
+
+ R = 64;
+ A = 64;
+ P = 64; //32
+
+ M = (freq * R) / 4; /* in Mhz */
+ N = (M - A * 1000) / (P * 1000);
+
+ reg1[1] |= (N >> 9) & 0x03;
+ reg1[2] = (N >> 1) & 0xff;
+ reg1[3] = (N << 7) & 0x80;
+
+ reg2[1] |= (R >> 8) & 0x03;
+ reg2[2] = R & 0xFF; /* R */
+
+ reg1[3] |= A & 0x7f; /* A */
+
+ if (P == 64)
+ reg1[1] |= 0x40; /* Prescaler 64/65 */
+
+ reg0[1] |= 0x03;
+
+ if ((err = pll_write(i2c, 0x60, reg0, sizeof(reg0))))
+ return err;
+
+ if ((err = pll_write(i2c, 0x60, reg1, sizeof(reg1))))
+ return err;
+
+ if ((err = pll_write(i2c, 0x60, reg2, sizeof(reg2))))
+ return err;
+
+ return 0;
+}
+
+
+static int pll_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq, int ftype, int srate)
+{
+ switch(ftype) {
+ case SAMSUNG_TBMU24112IMB:
+ return sl1935_set_tv_freq(i2c, freq, ftype);
+
+ case LG_TDQF_S001F:
+ return sl1935_set_tv_freq(i2c, freq, ftype);
+
+ case PHILIPS_SU1278_TUA:
+ return tua6100_set_tv_freq(i2c, freq, ftype, srate);
+
+ default:
+ return tsa5059_set_tv_freq(i2c, freq, ftype, srate);
+}
+}
+
+#if 0
+static int tsa5059_read_status (struct dvb_i2c_bus *i2c)
+{
+ int ret;
+ u8 rpt1 [] = { 0x05, 0xb5 };
+ u8 stat [] = { 0 };
+
+ struct i2c_msg msg [] = {{ .addr = 0x68, .flags = 0, .buf = rpt1, .len = 2 },
+ { .addr = 0x60, .flags = I2C_M_RD, .buf = stat, .len = 1 }};
+
+ dprintk ("%s\n", __FUNCTION__);
+
+ ret = i2c->xfer (i2c, msg, 2);
+
+ if (ret != 2)
+ dprintk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret);
+
+ return stat[0];
+}
+#endif
+
+
+static int stv0299_init (struct dvb_i2c_bus *i2c, int ftype)
+{
+ int i;
+
+ dprintk("stv0299: init chip\n");
+
+ switch(ftype) {
+ case SAMSUNG_TBMU24112IMB:
+ dprintk("%s: init stv0299 chip for Samsung TBMU24112IMB\n", __FUNCTION__);
+
+ for (i=0; i<sizeof(init_tab_samsung); i+=2)
+ {
+ dprintk("%s: reg == 0x%02x, val == 0x%02x\n", __FUNCTION__, init_tab_samsung[i], init_tab_samsung[i+1]);
+
+ stv0299_writereg (i2c, init_tab_samsung[i], init_tab_samsung[i+1]);
+ }
+ break;
+
+ case PHILIPS_SU1278_TSA_TT:
+ for (i=0; i<sizeof(init_tab_su1278_tsa_tt); i+=2) {
+ stv0299_writereg (i2c, init_tab_su1278_tsa_tt[i], init_tab_su1278_tsa_tt[i+1]);
+ }
+ break;
+
+ default:
+ stv0299_writereg (i2c, 0x01, 0x15);
+ stv0299_writereg (i2c, 0x02, ftype == PHILIPS_SU1278_TUA ? 0x00 : 0x30);
+ stv0299_writereg (i2c, 0x03, 0x00);
+
+ for (i=0; i<sizeof(init_tab); i+=2)
+ stv0299_writereg (i2c, init_tab[i], init_tab[i+1]);
+
+ /* AGC1 reference register setup */
+ if (ftype == PHILIPS_SU1278_TSA || ftype == PHILIPS_SU1278_TSA_TY)
+ stv0299_writereg (i2c, 0x0f, 0x92); /* Iagc = Inverse, m1 = 18 */
+ else if (ftype == PHILIPS_SU1278_TUA)
+ stv0299_writereg (i2c, 0x0f, 0x94); /* Iagc = Inverse, m1 = 20 */
+ else
+ stv0299_writereg (i2c, 0x0f, 0x52); /* Iagc = Normal, m1 = 18 */
+ break;
+ }
+
+ switch(stv0299_status) {
+ case STATUS_BER:
+ stv0299_writereg(i2c, 0x34, 0x93);
+ break;
+
+ case STATUS_UCBLOCKS:
+ stv0299_writereg(i2c, 0x34, 0xB3);
+ break;
+ }
+
+ return 0;
+}
+
+
+static int stv0299_set_FEC (struct dvb_i2c_bus *i2c, fe_code_rate_t fec)