+ hactive=720;
+ hblank=122;
+ vactive=487;
+ luma_lpf=1;
+ uv_lpf=1;
+
+ src_decimation=0x21f;
+ if (std == V4L2_STD_PAL_M) {
+ vblank=20;
+ vblank656=24;
+ burst=0x61;
+ comb=0x20;
+
+ sc=555452;
+ } else {
+ vblank=26;
+ vblank656=26;
+ burst=0x5b;
+ comb=0x66;
+ sc=556063;
+ }
+ }
+
+ /* DEBUG: Displays configured PLL frequency */
+ pll_int=cx25840_read(client, 0x108);
+ pll_frac=cx25840_read4(client, 0x10c)&0x1ffffff;
+ pll_post=cx25840_read(client, 0x109);
+ v4l_dbg(1, cx25840_debug, client,
+ "PLL regs = int: %u, frac: %u, post: %u\n",
+ pll_int,pll_frac,pll_post);
+
+ if (pll_post) {
+ int fin, fsc;
+ int pll= (28636363L*((((u64)pll_int)<<25L)+pll_frac)) >>25L;
+
+ pll/=pll_post;
+ v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
+ pll/1000000, pll%1000000);
+ v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
+ pll/8000000, (pll/8)%1000000);
+
+ fin=((u64)src_decimation*pll)>>12;
+ v4l_dbg(1, cx25840_debug, client, "ADC Sampling freq = "
+ "%d.%06d MHz\n",
+ fin/1000000,fin%1000000);
+
+ fsc= (((u64)sc)*pll) >> 24L;
+ v4l_dbg(1, cx25840_debug, client, "Chroma sub-carrier freq = "
+ "%d.%06d MHz\n",
+ fsc/1000000,fsc%1000000);
+
+ v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
+ "vblank %i , vactive %i, vblank656 %i, src_dec %i,"
+ "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x,"
+ " sc 0x%06x\n",
+ hblank, hactive, vblank, vactive, vblank656,
+ src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
+ }
+
+ /* Sets horizontal blanking delay and active lines */
+ cx25840_write(client, 0x470, hblank);
+ cx25840_write(client, 0x471, 0xff&(((hblank>>8)&0x3)|(hactive <<4)));
+ cx25840_write(client, 0x472, hactive>>4);
+
+ /* Sets burst gate delay */
+ cx25840_write(client, 0x473, burst);