- c->irq_mask = c->base.virt + 0x34;
- c->post_port = c->base.virt + 0x40;
- c->reply_port = c->base.virt + 0x44;
-
-#ifdef CONFIG_MTRR
- /* Enable Write Combining MTRR for IOP's memory region */
- c->mtrr_reg0 = mtrr_add(c->in_queue.phys, c->in_queue.len,
- MTRR_TYPE_WRCOMB, 1);
- c->mtrr_reg1 = -1;
-
- if (c->mtrr_reg0 < 0)
- printk(KERN_WARNING "%s: could not enable write combining "
- "MTRR\n", c->name);
- else
- printk(KERN_INFO "%s: using write combining MTRR\n", c->name);
-
- /*
- * If it is an INTEL i960 I/O processor then set the first 64K to
- * Uncacheable since the region contains the messaging unit which
- * shouldn't be cached.
- */
- if ((pdev->vendor == PCI_VENDOR_ID_INTEL ||
- pdev->vendor == PCI_VENDOR_ID_DPT) && !c->raptor) {
- printk(KERN_INFO "%s: MTRR workaround for Intel i960 processor"
- "\n", c->name);
- c->mtrr_reg1 = mtrr_add(c->base.phys, 0x10000,
- MTRR_TYPE_UNCACHABLE, 1);
-
- if (c->mtrr_reg1 < 0) {
- printk(KERN_WARNING "%s: Error in setting "
- "MTRR_TYPE_UNCACHABLE\n", c->name);
- mtrr_del(c->mtrr_reg0, c->in_queue.phys,
- c->in_queue.len);
- c->mtrr_reg0 = -1;
+ c->irq_status = c->base.virt + I2O_IRQ_STATUS;
+ c->irq_mask = c->base.virt + I2O_IRQ_MASK;
+ c->in_port = c->base.virt + I2O_IN_PORT;
+ c->out_port = c->base.virt + I2O_OUT_PORT;
+
+ /* Motorola/Freescale chip does not follow spec */
+ if (pdev->vendor == PCI_VENDOR_ID_MOTOROLA && pdev->device == 0x18c0) {
+ /* Check if CPU is enabled */
+ if (be32_to_cpu(readl(c->base.virt + 0x10000)) & 0x10000000) {
+ printk(KERN_INFO "%s: MPC82XX needs CPU running to "
+ "service I2O.\n", c->name);
+ i2o_pci_free(c);
+ return -ENODEV;
+ } else {
+ c->irq_status += I2O_MOTOROLA_PORT_OFFSET;
+ c->irq_mask += I2O_MOTOROLA_PORT_OFFSET;
+ c->in_port += I2O_MOTOROLA_PORT_OFFSET;
+ c->out_port += I2O_MOTOROLA_PORT_OFFSET;
+ printk(KERN_INFO "%s: MPC82XX workarounds activated.\n",
+ c->name);