- /* setup and enable chip select, MEM_STADDR1 */
- /* we really need to decode offsets only up till 0x20 */
- au_writel((1<<28) | (NAND_PHYS_ADDR>>4) |
- (((NAND_PHYS_ADDR + 0x1000)-1) & (0x3fff<<18)>>18),
- MEM_STADDR1);
- au_sync();
+ /* Locate NAND chip-select in order to determine NAND phys address */
+ mem_staddr = 0x00000000;
+ if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
+ mem_staddr = au_readl(MEM_STADDR0);
+ else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
+ mem_staddr = au_readl(MEM_STADDR1);
+ else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
+ mem_staddr = au_readl(MEM_STADDR2);
+ else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
+ mem_staddr = au_readl(MEM_STADDR3);
+
+ if (mem_staddr == 0x00000000) {
+ printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
+ kfree(au1550_mtd);
+ return 1;
+ }
+ nand_phys = (mem_staddr << 4) & 0xFFFC0000;
+
+ p_nand = (void __iomem *)ioremap(nand_phys, 0x1000);
+
+ /* make controller and MTD agree */
+ if (NAND_CS == 0)
+ nand_width = au_readl(MEM_STCFG0) & (1<<22);
+ if (NAND_CS == 1)
+ nand_width = au_readl(MEM_STCFG1) & (1<<22);
+ if (NAND_CS == 2)
+ nand_width = au_readl(MEM_STCFG2) & (1<<22);
+ if (NAND_CS == 3)
+ nand_width = au_readl(MEM_STCFG3) & (1<<22);