-Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
+Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
int options; /* Options enabled/disabled for the device */
unsigned long ext_phy_option;
int options; /* Options enabled/disabled for the device */
unsigned long ext_phy_option;
-
+ int ext_phy_addr;
+ u32 ext_phy_id;
+
struct amd8111e_link_config link_config;
int pm_cap;
struct amd8111e_link_config link_config;
int pm_cap;
- u32 pm_state[12];
struct net_device *next;
int mii;
struct mii_if_info mii_if;
#if AMD8111E_VLAN_TAG_USED
struct vlan_group *vlgrp;
struct net_device *next;
int mii;
struct mii_if_info mii_if;
#if AMD8111E_VLAN_TAG_USED
struct vlan_group *vlgrp;
-#endif
+#endif
char opened;
struct net_device_stats stats;
unsigned int drv_rx_errors;
struct dev_mc_list* mc_list;
struct amd8111e_coalesce_conf coal_conf;
char opened;
struct net_device_stats stats;
unsigned int drv_rx_errors;
struct dev_mc_list* mc_list;
struct amd8111e_coalesce_conf coal_conf;
- struct ipg_info ipg_data;
-
+ struct ipg_info ipg_data;
+
};
/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
BUG? */
#define amd8111e_writeq(_UlData,_memMap) \
writel(*(u32*)(&_UlData), _memMap); \
};
/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
BUG? */
#define amd8111e_writeq(_UlData,_memMap) \
writel(*(u32*)(&_UlData), _memMap); \
- writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
+ writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
/* maps the external speed options to internal value */
typedef enum {
/* maps the external speed options to internal value */