-#define SMC_CURRENT_BANK() SMC_inw( ioaddr, BANK_SELECT )
-#define SMC_SELECT_BANK(x) SMC_outw( x, ioaddr, BANK_SELECT )
-#define SMC_GET_BASE() SMC_inw( ioaddr, BASE_REG )
-#define SMC_SET_BASE(x) SMC_outw( x, ioaddr, BASE_REG )
-#define SMC_GET_CONFIG() SMC_inw( ioaddr, CONFIG_REG )
-#define SMC_SET_CONFIG(x) SMC_outw( x, ioaddr, CONFIG_REG )
-#define SMC_GET_COUNTER() SMC_inw( ioaddr, COUNTER_REG )
-#define SMC_GET_CTL() SMC_inw( ioaddr, CTL_REG )
-#define SMC_SET_CTL(x) SMC_outw( x, ioaddr, CTL_REG )
-#define SMC_GET_MII() SMC_inw( ioaddr, MII_REG )
-#define SMC_SET_MII(x) SMC_outw( x, ioaddr, MII_REG )
-#define SMC_GET_MIR() SMC_inw( ioaddr, MIR_REG )
-#define SMC_SET_MIR(x) SMC_outw( x, ioaddr, MIR_REG )
-#define SMC_GET_MMU_CMD() SMC_inw( ioaddr, MMU_CMD_REG )
-#define SMC_SET_MMU_CMD(x) SMC_outw( x, ioaddr, MMU_CMD_REG )
-#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
-#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
-#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
-#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
-#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
-#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )
-#define SMC_GET_RPC() SMC_inw( ioaddr, RPC_REG )
-#define SMC_SET_RPC(x) SMC_outw( x, ioaddr, RPC_REG )
-#define SMC_GET_TCR() SMC_inw( ioaddr, TCR_REG )
-#define SMC_SET_TCR(x) SMC_outw( x, ioaddr, TCR_REG )
+#define SMC_GET_INT_MASK() \
+ ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
+ : (SMC_inw( ioaddr, INT_REG ) >> 8) )
+
+#define SMC_SET_INT_MASK(x) \
+ do { \
+ if (SMC_CAN_USE_8BIT) \
+ SMC_outb(x, ioaddr, IM_REG); \
+ else \
+ SMC_outw((x) << 8, ioaddr, INT_REG); \
+ } while (0)
+
+#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
+
+#define SMC_SELECT_BANK(x) \
+ do { \
+ if (SMC_MUST_ALIGN_WRITE) \
+ SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
+ else \
+ SMC_outw(x, ioaddr, BANK_SELECT); \
+ } while (0)
+
+#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
+
+#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
+
+#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
+
+#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
+
+#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
+
+#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
+
+#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
+
+#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
+
+#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
+
+#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
+
+#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
+
+#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
+
+#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
+
+#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
+
+#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
+
+#define SMC_SET_PTR(x) \
+ do { \
+ if (SMC_MUST_ALIGN_WRITE) \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
+ else \
+ SMC_outw(x, ioaddr, PTR_REG); \
+ } while (0)
+
+#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
+
+#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
+
+#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
+
+#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
+
+#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
+
+#define SMC_SET_RPC(x) \
+ do { \
+ if (SMC_MUST_ALIGN_WRITE) \
+ SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
+ else \
+ SMC_outw(x, ioaddr, RPC_REG); \
+ } while (0)
+
+#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
+
+#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)