struct sunqe *qes[4]; /* Each child MACE */
unsigned int qec_bursts; /* Support burst sizes */
struct sbus_dev *qec_sdev; /* QEC's SBUS device */
struct sunqe *qes[4]; /* Each child MACE */
unsigned int qec_bursts; /* Support burst sizes */
struct sbus_dev *qec_sdev; /* QEC's SBUS device */
- unsigned long qcregs; /* QEC per-channel Registers */
- unsigned long mregs; /* Per-channel MACE Registers */
+ void __iomem *qcregs; /* QEC per-channel Registers */
+ void __iomem *mregs; /* Per-channel MACE Registers */
struct qe_init_block *qe_block; /* RX and TX descriptors */
__u32 qblock_dvma; /* RX and TX descriptors */
spinlock_t lock; /* Protects txfull state */
struct qe_init_block *qe_block; /* RX and TX descriptors */
__u32 qblock_dvma; /* RX and TX descriptors */
spinlock_t lock; /* Protects txfull state */