+ pci_read_config_byte(pdev, via->via_pci_superio_config_reg, &tmp);
+ tmp |= via->via_pci_superio_config_data;
+ pci_write_config_byte(pdev, via->via_pci_superio_config_reg, tmp);
+
+ /* Bits 1-0: Parallel Port Mode / Enable */
+ outb(via->viacfg_function, VIA_CONFIG_INDEX);
+ tmp = inb (VIA_CONFIG_DATA);
+ /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
+ outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
+ tmp2 = inb (VIA_CONFIG_DATA);
+ if (siofunc == VIA_FUNCTION_PROBE)
+ {
+ siofunc = tmp & VIA_FUNCTION_PARPORT_DISABLE;
+ ppcontrol = tmp2;
+ }
+ else
+ {
+ tmp &= ~VIA_FUNCTION_PARPORT_DISABLE;
+ tmp |= siofunc;
+ outb(via->viacfg_function, VIA_CONFIG_INDEX);
+ outb(tmp, VIA_CONFIG_DATA);
+ tmp2 &= ~(VIA_PARPORT_BIDIR|VIA_PARPORT_ECPEPP);
+ tmp2 |= ppcontrol;
+ outb(via->viacfg_parport_control, VIA_CONFIG_INDEX);
+ outb(tmp2, VIA_CONFIG_DATA);
+ }