+void
+qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
+{
+ uint32_t cnt;
+ char *uiter;
+ struct qla24xx_fw_dump *fw;
+ uint32_t ext_mem_cnt;
+
+ uiter = ha->fw_dump_buffer;
+ fw = ha->fw_dump24;
+
+ qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
+ ha->fw_major_version, ha->fw_minor_version,
+ ha->fw_subminor_version, ha->fw_attributes);
+
+ qla_uprintf(&uiter, "\nR2H Status Register\n%04x\n", fw->host_status);
+
+ qla_uprintf(&uiter, "\nHost Interface Registers");
+ for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nShadow Registers");
+ for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nMailbox Registers");
+ for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
+ for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
+ for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nCommand DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
+ for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
+ for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
+ for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nRISC GP Registers");
+ for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nLMC Registers");
+ for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
+ for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nFB Hardware Registers");
+ for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
+ if (cnt % 8 == 0)
+ qla_uprintf(&uiter, "\n");
+
+ qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nCode RAM");
+ for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
+ if (cnt % 8 == 0) {
+ qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
+ }
+ qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n\nExternal Memory");
+ ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
+ for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
+ if (cnt % 8 == 0) {
+ qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
+ }
+ qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
+ }
+
+ qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
+}
+
+