+ if (stat & HSR_RISC_PAUSED) {
+ hccr = RD_REG_WORD(®->hccr);
+ if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
+ qla_printk(KERN_INFO, ha,
+ "Parity error -- HCCR=%x.\n", hccr);
+ else
+ qla_printk(KERN_INFO, ha,
+ "RISC paused -- HCCR=%x\n", hccr);
+
+ /*
+ * Issue a "HARD" reset in order for the RISC
+ * interrupt bit to be cleared. Schedule a big
+ * hammmer to get out of the RISC PAUSED state.
+ */
+ WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
+ RD_REG_WORD(®->hccr);
+ set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
+ break;
+ } else if ((stat & HSR_RISC_INT) == 0)