+ pSRB->SGToBeXferLen = 0;
+ }
+ pSRB->SGToBeXferLen -= (pSRB->Saved_Ptr - pSRB->TotalXferredLen);
+ pSRB->SGBusAddr += (pSRB->Saved_Ptr - pSRB->TotalXferredLen);
+ printk (KERN_INFO "DC390: Pointer restored. Segment %i, Total %li, Bus %08lx\n",
+ pSRB->SGIndex, pSRB->Saved_Ptr, pSRB->SGBusAddr);
+
+ } else if(pcmd->request_buffer) {
+ //dc390_pci_sync(pSRB);
+
+ sg_dma_len(&pSRB->Segmentx) = pcmd->request_bufflen - pSRB->Saved_Ptr;
+ pSRB->SGcount = 1;
+ pSRB->pSegmentList = (struct scatterlist *) &pSRB->Segmentx;
+ } else {
+ pSRB->SGcount = 0;
+ printk (KERN_INFO "DC390: RESTORE_PTR message for Transfer without Scatter-Gather ??\n");
+ }
+
+ pSRB->TotalXferredLen = pSRB->Saved_Ptr;
+}
+
+
+/* According to the docs, the AM53C974 reads the message and
+ * generates a Successful Operation IRQ before asserting ACK for
+ * the last byte (how does it know whether it's the last ?) */
+/* The old code handled it in another way, indicating, that on
+ * every message byte an IRQ is generated and every byte has to
+ * be manually ACKed. Hmmm ? (KG, 98/11/28) */
+/* The old implementation was correct. Sigh! */
+
+/* Check if the message is complete */
+static u8 __inline__
+dc390_MsgIn_complete (u8 *msgbuf, u32 len)
+{
+ if (*msgbuf == EXTENDED_MESSAGE)
+ {
+ if (len < 2) return 0;
+ if (len < msgbuf[1] + 2) return 0;
+ }
+ else if (*msgbuf >= 0x20 && *msgbuf <= 0x2f) // two byte messages
+ if (len < 2) return 0;
+ return 1;
+}
+
+
+
+/* read and eval received messages */
+static void
+dc390_MsgIn_0( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ struct dc390_dcb* pDCB = pACB->pActiveDCB;
+
+ /* Read the msg */
+
+ pSRB->MsgInBuf[pACB->MsgLen++] = DC390_read8 (ScsiFifo);
+ //pSRB->SRBState = 0;
+
+ /* Msg complete ? */
+ if (dc390_MsgIn_complete (pSRB->MsgInBuf, pACB->MsgLen))
+ {
+ DEBUG0 (printk (KERN_INFO "DC390: MsgIn:"); dc390_printMsg (pSRB->MsgInBuf, pACB->MsgLen));
+ /* Now eval the msg */
+ switch (pSRB->MsgInBuf[0])
+ {
+ case DISCONNECT:
+ pSRB->SRBState = SRB_DISCONNECT; break;
+
+ case SIMPLE_QUEUE_TAG:
+ case HEAD_OF_QUEUE_TAG:
+ case ORDERED_QUEUE_TAG:
+ pSRB = dc390_MsgIn_QTag (pACB, pDCB, pSRB->MsgInBuf[1]);
+ break;
+
+ case MESSAGE_REJECT:
+ DC390_write8 (ScsiCmd, RESET_ATN_CMD);
+ pDCB->NegoPeriod = 50; /* 200ns <=> 5 MHz */
+ if( pSRB->SRBState & DO_SYNC_NEGO)
+ dc390_MsgIn_set_async (pACB, pSRB);
+ break;
+
+ case EXTENDED_MESSAGE:
+ /* reject every extended msg but SDTR */
+ if (pSRB->MsgInBuf[1] != 3 || pSRB->MsgInBuf[2] != EXTENDED_SDTR)
+ dc390_MsgIn_reject (pACB, pSRB);
+ else
+ {
+ if (pSRB->MsgInBuf[3] == 0 || pSRB->MsgInBuf[4] == 0)
+ dc390_MsgIn_set_async (pACB, pSRB);
+ else
+ dc390_MsgIn_set_sync (pACB, pSRB);
+ }
+
+ // nothing has to be done
+ case COMMAND_COMPLETE: break;
+
+ // SAVE POINTER may be ignored as we have the struct dc390_srb* associated with the
+ // scsi command. Thanks, Gerard, for pointing it out.
+ case SAVE_POINTERS:
+ pSRB->Saved_Ptr = pSRB->TotalXferredLen;
+ break;
+ // The device might want to restart transfer with a RESTORE
+ case RESTORE_POINTERS:
+ DEBUG0(printk ("DC390: RESTORE POINTER message received ... try to handle\n"));
+ dc390_restore_ptr (pACB, pSRB);
+ break;
+
+ // reject unknown messages
+ default: dc390_MsgIn_reject (pACB, pSRB);
+ }
+
+ /* Clear counter and MsgIn state */
+ pSRB->SRBState &= ~SRB_MSGIN;
+ pACB->MsgLen = 0;
+ }
+
+ *psstatus = SCSI_NOP0;
+ DC390_write8 (ScsiCmd, MSG_ACCEPTED_CMD);
+ //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
+}
+
+
+static void
+dc390_DataIO_Comm( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 ioDir)
+{
+ struct scatterlist *psgl;
+ unsigned long lval;
+ struct dc390_dcb* pDCB = pACB->pActiveDCB;
+
+ if (pSRB == pACB->pTmpSRB)
+ {
+ if (pDCB)
+ printk(KERN_ERR "DC390: pSRB == pTmpSRB! (TagQ Error?) (%02i-%i)\n", pDCB->TargetID, pDCB->TargetLUN);
+ else
+ printk(KERN_ERR "DC390: pSRB == pTmpSRB! (TagQ Error?) (DCB 0!)\n");
+
+ /* Try to recover - some broken disks react badly to tagged INQUIRY */
+ if (pDCB && pACB->scan_devices && pDCB->GoingSRBCnt == 1) {
+ pSRB = pDCB->pGoingSRB;
+ pDCB->pActiveSRB = pSRB;
+ } else {
+ pSRB->pSRBDCB = pDCB;
+ dc390_EnableMsgOut_Abort(pACB, pSRB);
+ if (pDCB)
+ pDCB->DCBFlag |= ABORT_DEV;
+ return;
+ }
+ }
+
+ if( pSRB->SGIndex < pSRB->SGcount )
+ {
+ DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir /* | DMA_INT */);
+ if( !pSRB->SGToBeXferLen )
+ {
+ psgl = pSRB->pSegmentList;
+ pSRB->SGBusAddr = cpu_to_le32(pci_dma_lo32(sg_dma_address(psgl)));
+ pSRB->SGToBeXferLen = cpu_to_le32(sg_dma_len(psgl));
+ DEBUG1(printk (KERN_DEBUG " DC390: Next SG segment."));
+ }
+ lval = pSRB->SGToBeXferLen;
+ DEBUG1(printk (KERN_DEBUG " DC390: Start transfer: %li bytes (address %08lx)\n", lval, pSRB->SGBusAddr));
+ DC390_write8 (CtcReg_Low, (u8) lval);
+ lval >>= 8;
+ DC390_write8 (CtcReg_Mid, (u8) lval);
+ lval >>= 8;
+ DC390_write8 (CtcReg_High, (u8) lval);
+
+ DC390_write32 (DMA_XferCnt, pSRB->SGToBeXferLen);
+ DC390_write32 (DMA_XferAddr, pSRB->SGBusAddr);
+
+ //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir); /* | DMA_INT; */
+ pSRB->SRBState = SRB_DATA_XFER;
+
+ DC390_write8 (ScsiCmd, DMA_COMMAND+INFO_XFER_CMD);
+
+ DC390_write8 (DMA_Cmd, DMA_START_CMD | ioDir | DMA_INT);
+ //DEBUG1(DC390_write32 (DMA_ScsiBusCtrl, WRT_ERASE_DMA_STAT | EN_INT_ON_PCI_ABORT));
+ //DEBUG1(printk (KERN_DEBUG "DC390: DMA_Status: %02x\n", DC390_read8 (DMA_Status)));
+ //DEBUG1(DC390_write32 (DMA_ScsiBusCtrl, EN_INT_ON_PCI_ABORT));
+ }
+ else /* xfer pad */
+ {
+ if( pSRB->SGcount )
+ {
+ pSRB->AdaptStatus = H_OVER_UNDER_RUN;
+ pSRB->SRBStatus |= OVER_RUN;
+ DEBUG0(printk (KERN_WARNING " DC390: Overrun -"));
+ }
+ DEBUG0(printk (KERN_WARNING " Clear transfer pad \n"));
+ DC390_write8 (CtcReg_Low, 0);
+ DC390_write8 (CtcReg_Mid, 0);
+ DC390_write8 (CtcReg_High, 0);
+
+ pSRB->SRBState |= SRB_XFERPAD;
+ DC390_write8 (ScsiCmd, DMA_COMMAND+XFER_PAD_BYTE);
+/*
+ DC390_write8 (DMA_Cmd, DMA_IDLE_CMD | ioDir); // | DMA_INT;
+ DC390_write8 (DMA_Cmd, DMA_START_CMD | ioDir | DMA_INT);
+*/
+ }
+}
+
+
+static void
+dc390_DataOutPhase( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ dc390_DataIO_Comm (pACB, pSRB, WRITE_DIRECTION);
+}
+
+static void
+dc390_DataInPhase( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ dc390_DataIO_Comm (pACB, pSRB, READ_DIRECTION);
+}
+
+static void
+dc390_CommandPhase( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ struct dc390_dcb* pDCB;
+ u8 i, cnt;
+ u8 *ptr;
+
+ DC390_write8 (ScsiCmd, RESET_ATN_CMD);
+ DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
+ if( !(pSRB->SRBFlag & AUTO_REQSENSE) )
+ {
+ cnt = (u8) pSRB->pcmd->cmd_len;
+ ptr = (u8 *) pSRB->pcmd->cmnd;
+ for(i=0; i < cnt; i++)
+ DC390_write8 (ScsiFifo, *(ptr++));
+ }
+ else
+ {
+ DC390_write8 (ScsiFifo, REQUEST_SENSE);
+ pDCB = pACB->pActiveDCB;
+ DC390_write8 (ScsiFifo, pDCB->TargetLUN << 5);
+ DC390_write8 (ScsiFifo, 0);
+ DC390_write8 (ScsiFifo, 0);
+ DC390_write8 (ScsiFifo, sizeof(pSRB->pcmd->sense_buffer));
+ DC390_write8 (ScsiFifo, 0);
+ DEBUG0(printk(KERN_DEBUG "DC390: AutoReqSense (CmndPhase)!\n"));
+ }
+ pSRB->SRBState = SRB_COMMAND;
+ DC390_write8 (ScsiCmd, INFO_XFER_CMD);
+}
+
+static void
+dc390_StatusPhase( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
+ pSRB->SRBState = SRB_STATUS;
+ DC390_write8 (ScsiCmd, INITIATOR_CMD_CMPLTE);
+ //DC390_write8 (DMA_Cmd, DMA_IDLE_CMD);
+}
+
+static void
+dc390_MsgOutPhase( struct dc390_acb* pACB, struct dc390_srb* pSRB, u8 *psstatus)
+{
+ u8 bval, i, cnt;
+ u8 *ptr;
+ struct dc390_dcb* pDCB;
+
+ DC390_write8 (ScsiCmd, CLEAR_FIFO_CMD);
+ pDCB = pACB->pActiveDCB;
+ if( !(pSRB->SRBState & SRB_MSGOUT) )
+ {
+ cnt = pSRB->MsgCnt;
+ if( cnt )
+ {
+ ptr = (u8 *) pSRB->MsgOutBuf;
+ for(i=0; i < cnt; i++)
+ DC390_write8 (ScsiFifo, *(ptr++));
+ pSRB->MsgCnt = 0;
+ if( (pDCB->DCBFlag & ABORT_DEV_) &&
+ (pSRB->MsgOutBuf[0] == ABORT) )
+ pSRB->SRBState = SRB_ABORT_SENT;
+ }
+ else
+ {
+ bval = ABORT; /* ??? MSG_NOP */
+ if( (pSRB->pcmd->cmnd[0] == INQUIRY ) ||
+ (pSRB->pcmd->cmnd[0] == REQUEST_SENSE) ||
+ (pSRB->SRBFlag & AUTO_REQSENSE) )