+#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
+ {
+ .port = {
+ .membase = (void *)0xff923000,
+ .mapbase = 0xff923000,
+ .iotype = UPIO_MEM,
+ .irq = 61,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xff924000,
+ .mapbase = 0xff924000,
+ .iotype = UPIO_MEM,
+ .irq = 62,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF1_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xff925000,
+ .mapbase = 0xff925000,
+ .iotype = UPIO_MEM,
+ .irq = 63,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 2,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7770_SCIF2_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+ {
+ .port = {
+ .membase = (void *)0xffe00000,
+ .mapbase = 0xffe00000,
+ .iotype = UPIO_MEM,
+ .irq = 43,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7780_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+ {
+ .port = {
+ .membase = (void *)0xffe10000,
+ .mapbase = 0xffe10000,
+ .iotype = UPIO_MEM,
+ .irq = 79,
+ .ops = &sci_uart_ops,
+ .flags = UPF_BOOT_AUTOCONF,
+ .line = 1,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7780_SCIF1_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },