+#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
+ {
+ .port = {
+ .membase = (void *)0xA4430000,
+ .mapbase = 0xA4430000,
+ .iotype = SERIAL_IO_MEM,
+ .irq = 25,
+ .ops = &sci_uart_ops,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH7300_SCIF0_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
+ {
+ .port = {
+ .membase = (void *)0xffe00000,
+ .mapbase = 0xffe00000,
+ .iotype = SERIAL_IO_MEM,
+ .irq = 25,
+ .ops = &sci_uart_ops,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH73180_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },
+#elif defined(CONFIG_SH_RTS7751R2D)
+ {
+ .port = {
+ .membase = (void *)0xffe80000,
+ .mapbase = 0xffe80000,
+ .iotype = SERIAL_IO_MEM,
+ .irq = 43,
+ .ops = &sci_uart_ops,
+ .flags = ASYNC_BOOT_AUTOCONF,
+ .line = 0,
+ },
+ .type = PORT_SCIF,
+ .irqs = SH4_SCIF_IRQS,
+ .init_pins = sci_init_pins_scif,
+ },