- switch (par->riva.Architecture) {
-#if 0 /* no support yet for other nVidia chipsets */
- par->chan[2].ddc_base = 0x50;
- riva_setup_i2c_bus(&par->chan[2], "BUS2");
-#endif
- case NV_ARCH_10:
- case NV_ARCH_20:
- case NV_ARCH_04:
- par->chan[1].ddc_base = 0x36;
- riva_setup_i2c_bus(&par->chan[1], "BUS1");
- case NV_ARCH_03:
- par->chan[0].ddc_base = 0x3e;
- riva_setup_i2c_bus(&par->chan[0], "BUS0");
- }
+ par->chan[0].ddc_base = 0x3e;
+ par->chan[1].ddc_base = 0x36;
+ par->chan[2].ddc_base = 0x50;
+ riva_setup_i2c_bus(&par->chan[0], "BUS1");
+ riva_setup_i2c_bus(&par->chan[1], "BUS2");
+ riva_setup_i2c_bus(&par->chan[2], "BUS3");