- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
- .lccr3 = LCCR3_ACBsDiv(512),
-};
-#endif
-
-#ifdef CONFIG_SA1100_OMNIMETER
-static struct sa1100fb_mach_info omnimeter_info __initdata = {
- .pixclock = 0, .bpp = 4,
- .xres = 480, .yres = 320,
-
- .hsync_len = 1, .vsync_len = 1,
- .left_margin = 10, .upper_margin = 0,
- .right_margin = 10, .lower_margin = 0,
-
- .cmap_greyscale = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_8PixMono,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(255) |
- LCCR3_PixClkDiv(44),
-#error FIXME: fix pixclock, ACBsDiv
- /*
- * FIXME: I think ACBsDiv is wrong above - should it be 512 (disabled)?
- * - rmk
- */
-};
-#endif
-
-#ifdef CONFIG_SA1100_PANGOLIN
-static struct sa1100fb_mach_info pangolin_info __initdata = {
- .pixclock = 341521, .bpp = 16,
- .xres = 800, .yres = 600,
-
- .hsync_len = 64, .vsync_len = 7,
- .left_margin = 160, .upper_margin = 7,
- .right_margin = 24, .lower_margin = 1,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsCntOff,
-};
-#endif
-
-#ifdef CONFIG_SA1100_STORK
-#if STORK_TFT /* ie the NEC TFT */
-/*
- * pixclock is ps per clock. say 72Hz, 800x600 clocks => (1/72)/(800*600)
- * = 28935 and a bit
- * NB likely to be increased to ease bus timings wrt pcmcia interface
- */
-static struct sa1100fb_mach_info stork_tft_info __initdata = {
- .pixclock = 28935, .bpp = 16,
- .xres = 640, .yres = 480,
-
- .hsync_len = 64, .vsync_len = 2,
- .left_margin = 48, .upper_margin = 12,
- .right_margin = 48, .lower_margin = 31,
-
- .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
- .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsCntOff,
-};
-
-static struct sa1100fb_rgb stork_tft_rgb_16 = {
- .red = { .offset = 11, .length = 5, },
- .green = { .offset = 5, .length = 6, },
- .blue = { .offset = 0, .length = 5, },
- .transp = { .offset = 0, .length = 0, },
-};
-
-#else /* Kyocera DSTN */
-
-static struct sa1100fb_mach_info stork_dstn_info __initdata = {
- .pixclock = 0, .bpp = 16,
- .xres = 640, .yres = 480,
-
- .hsync_len = 2, .vsync_len = 2,
- .left_margin = 2, .upper_margin = 0,
- .right_margin = 2, .lower_margin = 0,
-
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT ,
-
- .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
-#error Fixme
- .lccr3 = 0xff00 |
- 0x18 /* ought to be 0x14 but DMA isn't up to that as yet */
-};
-
-static struct sa1100fb_rgb stork_dstn_rgb_16 = {
- .red = { .offset = 8, .length = 4, },
- .green = { .offset = 4, .length = 4, },
- .blue = { .offset = 0, .length = 4, },
- .transp = { .offset = 0, .length = 0, },
-};
-#endif
-#endif
-
-#ifdef CONFIG_SA1100_PT_SYSTEM3
-/*
- * 648 x 480 x 8bpp x 75Hz Dual Panel Color STN Display
- *
- * pixclock = 1/( 640*3/8*240 ), [pixclock]=1e-12s=ps
- * 3 due to r,g,b lines
- * 8 due to 8 bit data bus
- * 640 due to 640 pixels per line
- * 240 = 480/2 due to dual panel display
- * =>4.32Mhz => 231481E-12s
- */
-static struct sa1100fb_mach_info system3_info __initdata = {
- .pixclock = 231481, .bpp = 8,
- .xres = 640, .yres = 480,
-
- .hsync_len = 2, .vsync_len = 2,
- .left_margin = 2, .upper_margin = 0,
- .right_margin = 2, .lower_margin = 0,
-