-#define orSISREG(base,val) do { \
- u8 __Temp = inb(base); \
- outSISREG(base, __Temp | (val)); \
- } while (0)
-#define andSISREG(base,val) do { \
- u8 __Temp = inb(base); \
- outSISREG(base, __Temp & (val)); \
- } while (0)
-#define inSISIDXREG(base,idx,var) do { \
- outb(idx,base); var=inb((base)+1); \
- } while (0)
-#define outSISIDXREG(base,idx,val) do { \
- outb(idx,base); outb((val),(base)+1); \
- } while (0)
-#define orSISIDXREG(base,idx,val) do { \
- u8 __Temp; \
- outb(idx,base); \
- __Temp = inb((base)+1)|(val); \
- outSISIDXREG(base,idx,__Temp); \
- } while (0)
-#define andSISIDXREG(base,idx,and) do { \
- u8 __Temp; \
- outb(idx,base); \
- __Temp = inb((base)+1)&(and); \
- outSISIDXREG(base,idx,__Temp); \
- } while (0)
-#define setSISIDXREG(base,idx,and,or) do { \
- u8 __Temp; \
- outb(idx,base); \
- __Temp = (inb((base)+1)&(and))|(or); \
- outSISIDXREG(base,idx,__Temp); \
- } while (0)
+
+#define orSISREG(base,val) \
+ do { \
+ u8 __Temp = inSISREG(base); \
+ outSISREG(base, __Temp | (val)); \
+ } while (0)
+
+#define andSISREG(base,val) \
+ do { \
+ u8 __Temp = inSISREG(base); \
+ outSISREG(base, __Temp & (val)); \
+ } while (0)
+
+#define inSISIDXREG(base,idx,var) \
+ do { \
+ outSISREG(base, idx); \
+ var = inSISREG((base)+1); \
+ } while (0)
+
+#define outSISIDXREG(base,idx,val) \
+ do { \
+ outSISREG(base, idx); \
+ outSISREG((base)+1, val); \
+ } while (0)
+
+#define orSISIDXREG(base,idx,val) \
+ do { \
+ u8 __Temp; \
+ outSISREG(base, idx); \
+ __Temp = inSISREG((base)+1) | (val); \
+ outSISREG((base)+1, __Temp); \
+ } while (0)
+
+#define andSISIDXREG(base,idx,and) \
+ do { \
+ u8 __Temp; \
+ outSISREG(base, idx); \
+ __Temp = inSISREG((base)+1) & (and); \
+ outSISREG((base)+1, __Temp); \
+ } while (0)
+
+#define setSISIDXREG(base,idx,and,or) \
+ do { \
+ u8 __Temp; \
+ outSISREG(base, idx); \
+ __Temp = (inSISREG((base)+1) & (and)) | (or); \
+ outSISREG((base)+1, __Temp); \
+ } while (0)