-struct
-{
- struct acpi_table_header header; /* table header */
- u32 reserved_pad; /* IA64 alignment, must be 0 */
- u64 firmware_ctrl; /* 64-bit Physical address of FACS */
- u64 dsdt; /* 64-bit Physical address of DSDT */
- u8 model; /* System Interrupt Model */
- u8 address_space; /* Address Space Bitmask */
- u16 sci_int; /* System vector of SCI interrupt */
- u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */
- u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */
- u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- u8 reserved2; /* reserved - must be zero */
- u64 smi_cmd; /* Port address of SMI command port */
- u64 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- u64 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- u64 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- u64 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- u64 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- u64 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- u64 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- u64 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
- u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- u8 gpe1_base; /* offset in gpe model where gpe1 events start */
- u8 reserved3; /* reserved */
- u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */
- u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */
- u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */
- u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */
- u8 century; /* index to century in RTC CMOS RAM */
- u8 reserved4; /* reserved */
- u32 flush_cash : 1; /* PAL_FLUSH_CACHE is correctly supported */
- u32 reserved5 : 1; /* reserved - must be zero */
- u32 proc_c1 : 1; /* all processors support C1 state */
- u32 plvl2_up : 1; /* C2 state works on MP system */
- u32 pwr_button : 1; /* Power button is handled as a generic feature */
- u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
- u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
- u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
- u32 tmr_val_ext : 1; /* tmr_val is 32 bits */
- u32 dock_cap : 1; /* Supports Docking */
- u32 reserved6 : 22; /* reserved - must be zero */
+struct {
+ struct acpi_table_header header; /* table header */
+ u32 reserved_pad; /* IA64 alignment, must be 0 */
+ u64 firmware_ctrl; /* 64-bit Physical address of FACS */
+ u64 dsdt; /* 64-bit Physical address of DSDT */
+ u8 model; /* System Interrupt Model */
+ u8 address_space; /* Address Space Bitmask */
+ u16 sci_int; /* System vector of SCI interrupt */
+ u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */
+ u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */
+ u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
+ u8 reserved2; /* reserved - must be zero */
+ u64 smi_cmd; /* Port address of SMI command port */
+ u64 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
+ u64 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
+ u64 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
+ u64 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
+ u64 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
+ u64 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
+ u64 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
+ u64 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
+ u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
+ u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
+ u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
+ u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
+ u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
+ u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
+ u8 gpe1_base; /* offset in gpe model where gpe1 events start */
+ u8 reserved3; /* reserved */
+ u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */
+ u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */
+ u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */
+ u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */
+ u8 century; /* index to century in RTC CMOS RAM */
+ u8 reserved4; /* reserved */
+ u32 flush_cash:1; /* PAL_FLUSH_CACHE is correctly supported */
+ u32 reserved5:1; /* reserved - must be zero */
+ u32 proc_c1:1; /* all processors support C1 state */
+ u32 plvl2_up:1; /* C2 state works on MP system */
+ u32 pwr_button:1; /* Power button is handled as a generic feature */
+ u32 sleep_button:1; /* Sleep button is handled as a generic feature, or not present */
+ u32 fixed_rTC:1; /* RTC wakeup stat not in fixed register space */
+ u32 rtcs4:1; /* RTC wakeup stat not possible from S4 */
+ u32 tmr_val_ext:1; /* tmr_val is 32 bits */
+ u32 dock_cap:1; /* Supports Docking */
+ u32 reserved6:22; /* reserved - must be zero */