-#define OMAP_32kHz_TIMER_BASE 0xfffb9000
-
-/* 32k Timer Registers */
-#define TIMER32k_CR 0x08
-#define TIMER32k_TVR 0x00
-#define TIMER32k_TCR 0x04
-
-/* 32k Timer Control Register definition */
-#define TIMER32k_TSS (1<<0)
-#define TIMER32k_TRB (1<<1)
-#define TIMER32k_INT (1<<2)
-#define TIMER32k_ARL (1<<3)
-
-/* MPU Timer base addresses */
-#define OMAP_TIMER1_BASE (0xfffec500)
-#define OMAP_TIMER2_BASE (0xfffec600)
-#define OMAP_TIMER3_BASE (0xfffec700)
-#define OMAP_MPUTIMER_BASE OMAP_TIMER1_BASE
-#define OMAP_MPUTIMER_OFFSET 0x100
-
-/* MPU Timer Registers */
-#define OMAP_TIMER1_CNTL (OMAP_TIMER_BASE1 + 0x0)
-#define OMAP_TIMER1_LOAD_TIM (OMAP_TIMER_BASE1 + 0x4)
-#define OMAP_TIMER1_READ_TIM (OMAP_TIMER_BASE1 + 0x8)
-
-#define OMAP_TIMER2_CNTL (OMAP_TIMER_BASE2 + 0x0)
-#define OMAP_TIMER2_LOAD_TIM (OMAP_TIMER_BASE2 + 0x4)
-#define OMAP_TIMER2_READ_TIM (OMAP_TIMER_BASE2 + 0x8)
-
-#define OMAP_TIMER3_CNTL (OMAP_TIMER_BASE3 + 0x0)
-#define OMAP_TIMER3_LOAD_TIM (OMAP_TIMER_BASE3 + 0x4)
-#define OMAP_TIMER3_READ_TIM (OMAP_TIMER_BASE3 + 0x8)
-
-/* CNTL_TIMER register bits */
-#define MPUTIM_FREE (1<<6)
-#define MPUTIM_CLOCK_ENABLE (1<<5)
-#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
-#define MPUTIM_PTV_BIT 2
-#define MPUTIM_AR (1<<1)
-#define MPUTIM_ST (1<<0)