-/* ce_lsiX_gb_cfg1 register bit masks & shifts */
-#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT 0
-#define CE_LSI_GB_CFG1_RXL0S_THS_MASK (0xffULL << 0)
-#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT 8
-#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK (0xfULL << 8);
-#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT 12
-#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK (0x7ULL << 12)
-#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT 15
-#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK (0x1ULL << 15)
-#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT 16
-#define CE_LSI_GB_CFG1_LPBK_SEL_MASK (0x3ULL << 16)
-#define CE_LSI_GB_CFG1_LPBK_EN_SHFT 18
-#define CE_LSI_GB_CFG1_LPBK_EN_MASK (0x1ULL << 18)
-#define CE_LSI_GB_CFG1_RVRS_LB_SHFT 19
-#define CE_LSI_GB_CFG1_RVRS_LB_MASK (0x1ULL << 19)
-#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT 20
-#define CE_LSI_GB_CFG1_RVRS_CLK_MASK (0x3ULL << 20)
-#define CE_LSI_GB_CFG1_SLF_TS_SHFT 24
-#define CE_LSI_GB_CFG1_SLF_TS_MASK (0xfULL << 24)