+/*
+ * SDRAM configuration registers.
+ */
+#ifdef CONFIG_M5271
+#define MCFSIM_DCR 0x40 /* SDRAM control */
+#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */
+#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */
+#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */
+#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
+#endif
+#ifdef CONFIG_M5275
+#define MCFSIM_DMR 0x40 /* SDRAM mode */
+#define MCFSIM_DCR 0x44 /* SDRAM control */
+#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */
+#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */
+#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */
+#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */
+#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */
+#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
+#endif
+
+/*
+ * GPIO pins setups to enable the UARTs.
+ */
+#ifdef CONFIG_M5271
+#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x0ff0
+#define UART2_ENABLE_MASK 0x3000
+#endif
+#ifdef CONFIG_M5275
+#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
+#define UART0_ENABLE_MASK 0x000f
+#define UART1_ENABLE_MASK 0x00f0
+#define UART2_ENABLE_MASK 0x3f00
+#endif
+