- * What is needed to separate a move to cp0 from a subsequent read from the
- * same cp0 register?
- */
-#ifdef CONFIG_CPU_MIPSR2
-
-__asm__(" .macro back_to_back_c0_hazard \n"
- " _ehb \n"
- " .endm \n");
-
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
- defined(CONFIG_CPU_SB1)
-
-__asm__(" .macro back_to_back_c0_hazard \n"
- " .endm \n");
-
-#else
-
-__asm__(" .macro back_to_back_c0_hazard \n"
- " .set noreorder \n"
- " _ssnop \n"
- " _ssnop \n"
- " _ssnop \n"
- " .set reorder \n"
- " .endm");
-
-#endif
-
-#define back_to_back_c0_hazard() \
- __asm__ __volatile__("back_to_back_c0_hazard")
-
-
-/*
- * Instruction execution hazard
- */
-#ifdef CONFIG_CPU_MIPSR2
-/*
- * gcc has a tradition of misscompiling the previous construct using the
- * address of a label as argument to inline assembler. Gas otoh has the
- * annoying difference between la and dla which are only usable for 32-bit
- * rsp. 64-bit code, so can't be used without conditional compilation.
- * The alterantive is switching the assembler to 64-bit code which happens
- * to work right even for 32-bit code ...
+ * The taken branch will result in a two cycle penalty for the two killed
+ * instructions on R4000 / R4400. Other processors only have a single cycle
+ * hazard so this is nice trick to have an optimal code for a range of
+ * processors.