+/*
+ * mtc0->mfc0 hazard
+ * The 24K has a 2 cycle mtc0/mfc0 execution hazard.
+ * It is a MIPS32R2 processor so ehb will clear the hazard.
+ */
+
+#ifdef CONFIG_CPU_MIPSR2
+/*
+ * Use a macro for ehb unless explicit support for MIPSR2 is enabled
+ */
+__asm__(
+ " .macro ehb \n\t"
+ " sll $0, $0, 3 \n\t"
+ " .endm \n\t"
+ " \n\t"
+ " .macro\tirq_enable_hazard \n\t"
+ " ehb \n\t"
+ " .endm \n\t"
+ " \n\t"
+ " .macro\tirq_disable_hazard \n\t"
+ " ehb \n\t"
+ " .endm");
+
+#define irq_enable_hazard() \
+ __asm__ __volatile__( \
+ "ehb\t\t\t\t# irq_enable_hazard")
+
+#define irq_disable_hazard() \
+ __asm__ __volatile__( \
+ "ehb\t\t\t\t# irq_disable_hazard")
+
+#elif defined(CONFIG_CPU_R10000)
+
+/*
+ * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
+ */
+
+__asm__(
+ " .macro\tirq_enable_hazard \n\t"
+ " .endm \n\t"
+ " \n\t"
+ " .macro\tirq_disable_hazard \n\t"
+ " .endm");
+
+#define irq_enable_hazard() do { } while (0)
+#define irq_disable_hazard() do { } while (0)
+
+#else
+
+/*
+ * Default for classic MIPS processors. Assume worst case hazards but don't
+ * care about the irq_enable_hazard - sooner or later the hardware will
+ * enable it and we don't care when exactly.
+ */
+
+__asm__(
+ " .macro _ssnop \n\t"
+ " sll $0, $2, 1 \n\t"
+ " .endm \n\t"
+ " \n\t"
+ " # \n\t"
+ " # There is a hazard but we do not care \n\t"
+ " # \n\t"
+ " .macro\tirq_enable_hazard \n\t"
+ " .endm \n\t"
+ " \n\t"
+ " .macro\tirq_disable_hazard \n\t"
+ " _ssnop; _ssnop; _ssnop \n\t"
+ " .endm");
+
+#define irq_enable_hazard() do { } while (0)
+#define irq_disable_hazard() \
+ __asm__ __volatile__( \
+ "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
+
+#endif
+