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linux 2.6.16.38 w/ vs2.0.3-rc1
[linux-2.6.git]
/
include
/
asm-mips
/
interrupt.h
diff --git
a/include/asm-mips/interrupt.h
b/include/asm-mips/interrupt.h
index
4bb9c06
..
50baf6b
100644
(file)
--- a/
include/asm-mips/interrupt.h
+++ b/
include/asm-mips/interrupt.h
@@
-19,13
+19,10
@@
__asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#ifdef CONFIG_MIPS_MT_SMTC
- " mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
- " ori $1, 0x400 \n"
- " xori $1, 0x400 \n"
- " mtc0 $1, $2, 1 \n"
-#elif defined(CONFIG_CPU_MIPSR2)
+#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" ei \n"
" ei \n"
+ " .set mips0 \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
@@
-67,13
+64,10
@@
__asm__ (
" .macro local_irq_disable\n"
" .set push \n"
" .set noat \n"
" .macro local_irq_disable\n"
" .set push \n"
" .set noat \n"
-#ifdef CONFIG_MIPS_MT_SMTC
- " mfc0 $1, $2, 1 \n"
- " ori $1, 0x400 \n"
- " .set noreorder \n"
- " mtc0 $1, $2, 1 \n"
-#elif defined(CONFIG_CPU_MIPSR2)
+#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" di \n"
" di \n"
+ " .set mips0 \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
#else
" mfc0 $1,$12 \n"
" ori $1,0x1f \n"
@@
-98,11
+92,7
@@
__asm__ (
" .macro local_save_flags flags \n"
" .set push \n"
" .set reorder \n"
" .macro local_save_flags flags \n"
" .set push \n"
" .set reorder \n"
-#ifdef CONFIG_MIPS_MT_SMTC
- " mfc0 \\flags, $2, 1 \n"
-#else
" mfc0 \\flags, $12 \n"
" mfc0 \\flags, $12 \n"
-#endif
" .set pop \n"
" .endm \n");
" .set pop \n"
" .endm \n");
@@
-116,15
+106,11
@@
__asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#ifdef CONFIG_MIPS_MT_SMTC
- " mfc0 \\result, $2, 1 \n"
- " ori $1, \\result, 0x400 \n"
- " .set noreorder \n"
- " mtc0 $1, $2, 1 \n"
- " andi \\result, \\result, 0x400 \n"
-#elif defined(CONFIG_CPU_MIPSR2)
+#ifdef CONFIG_CPU_MIPSR2
+ " .set mips32r2 \n"
" di \\result \n"
" andi \\result, 1 \n"
" di \\result \n"
" andi \\result, 1 \n"
+ " .set mips0 \n"
#else
" mfc0 \\result, $12 \n"
" ori $1, \\result, 0x1f \n"
#else
" mfc0 \\result, $12 \n"
" ori $1, \\result, 0x1f \n"
@@
-148,21
+134,16
@@
__asm__ (
" .set push \n"
" .set noreorder \n"
" .set noat \n"
" .set push \n"
" .set noreorder \n"
" .set noat \n"
-#ifdef CONFIG_MIPS_MT_SMTC
- "mfc0 $1, $2, 1 \n"
- "andi \\flags, 0x400 \n"
- "ori $1, 0x400 \n"
- "xori $1, 0x400 \n"
- "or \\flags, $1 \n"
- "mtc0 \\flags, $2, 1 \n"
-#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
+#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
/*
* Slow, but doesn't suffer from a relativly unlikely race
* condition we're having since days 1.
*/
/*
* Slow, but doesn't suffer from a relativly unlikely race
* condition we're having since days 1.
*/
+ " .set mips32r2 \n"
" beqz \\flags, 1f \n"
" di \n"
" ei \n"
" beqz \\flags, 1f \n"
" di \n"
" ei \n"
+ " .set mips0 \n"
"1: \n"
#elif defined(CONFIG_CPU_MIPSR2)
/*
"1: \n"
#elif defined(CONFIG_CPU_MIPSR2)
/*
@@
-194,29
+175,11
@@
do { \
: "memory"); \
} while(0)
: "memory"); \
} while(0)
-static inline int irqs_disabled(void)
-{
-#ifdef CONFIG_MIPS_MT_SMTC
- /*
- * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
- */
- unsigned long __result;
-
- __asm__ __volatile__(
- " .set noreorder \n"
- " mfc0 %0, $2, 1 \n"
- " andi %0, 0x400 \n"
- " slt %0, $0, %0 \n"
- " .set reorder \n"
- : "=r" (__result));
-
- return __result;
-#else
- unsigned long flags;
- local_save_flags(flags);
-
- return !(flags & 1);
-#endif
-}
+#define irqs_disabled() \
+({ \
+ unsigned long flags; \
+ local_save_flags(flags); \
+ !(flags & 1); \
+})
#endif /* _ASM_INTERRUPT_H */
#endif /* _ASM_INTERRUPT_H */