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linux 2.6.16.38 w/ vs2.0.3-rc1
[linux-2.6.git]
/
include
/
asm-powerpc
/
spu.h
diff --git
a/include/asm-powerpc/spu.h
b/include/asm-powerpc/spu.h
index
7cfcff3
..
38bacf2
100644
(file)
--- a/
include/asm-powerpc/spu.h
+++ b/
include/asm-powerpc/spu.h
@@
-110,14
+110,12
@@
struct spu {
char *name;
unsigned long local_store_phys;
u8 *local_store;
char *name;
unsigned long local_store_phys;
u8 *local_store;
- unsigned long problem_phys;
struct spu_problem __iomem *problem;
struct spu_priv1 __iomem *priv1;
struct spu_priv2 __iomem *priv2;
struct list_head list;
struct list_head sched_list;
int number;
struct spu_problem __iomem *problem;
struct spu_priv1 __iomem *priv1;
struct spu_priv2 __iomem *priv2;
struct list_head list;
struct list_head sched_list;
int number;
- int nid;
u32 isrc;
u32 node;
u64 flags;
u32 isrc;
u32 node;
u64 flags;
@@
-139,7
+137,6
@@
struct spu {
void (* wbox_callback)(struct spu *spu);
void (* ibox_callback)(struct spu *spu);
void (* stop_callback)(struct spu *spu);
void (* wbox_callback)(struct spu *spu);
void (* ibox_callback)(struct spu *spu);
void (* stop_callback)(struct spu *spu);
- void (* mfc_callback)(struct spu *spu);
char irq_c0[8];
char irq_c1[8];
char irq_c0[8];
char irq_c1[8];
@@
-152,14
+149,6
@@
int spu_irq_class_0_bottom(struct spu *spu);
int spu_irq_class_1_bottom(struct spu *spu);
void spu_irq_setaffinity(struct spu *spu, int cpu);
int spu_irq_class_1_bottom(struct spu *spu);
void spu_irq_setaffinity(struct spu *spu, int cpu);
-/* system callbacks from the SPU */
-struct spu_syscall_block {
- u64 nr_ret;
- u64 parm[6];
-};
-extern long spu_sys_callback(struct spu_syscall_block *s);
-
-/* syscalls implemented in spufs */
extern struct spufs_calls {
asmlinkage long (*create_thread)(const char __user *name,
unsigned int flags, mode_t mode);
extern struct spufs_calls {
asmlinkage long (*create_thread)(const char __user *name,
unsigned int flags, mode_t mode);
@@
-410,6
+399,7
@@
struct spu_priv1 {
#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
+
/* Interrupt Area */
u64 int_mask_RW[3]; /* 0x100 */
#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
/* Interrupt Area */
u64 int_mask_RW[3]; /* 0x100 */
#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L