- volatile u32 jtag_id; /* MBAR_CDM + 0x00 reg0 read only */
- volatile u32 rstcfg; /* MBAR_CDM + 0x04 reg1 read only */
- volatile u32 breadcrumb; /* MBAR_CDM + 0x08 reg2 */
-
- volatile u8 mem_clk_sel; /* MBAR_CDM + 0x0c reg3 byte0 */
- volatile u8 xlb_clk_sel; /* MBAR_CDM + 0x0d reg3 byte1 read only */
- volatile u8 ipb_clk_sel; /* MBAR_CDM + 0x0e reg3 byte2 */
- volatile u8 pci_clk_sel; /* MBAR_CDM + 0x0f reg3 byte3 */
-
- volatile u8 ext_48mhz_en; /* MBAR_CDM + 0x10 reg4 byte0 */
- volatile u8 fd_enable; /* MBAR_CDM + 0x11 reg4 byte1 */
- volatile u16 fd_counters; /* MBAR_CDM + 0x12 reg4 byte2,3 */
-
- volatile u32 clk_enables; /* MBAR_CDM + 0x14 reg5 */
-
- volatile u8 osc_disable; /* MBAR_CDM + 0x18 reg6 byte0 */
- volatile u8 reserved0[3]; /* MBAR_CDM + 0x19 reg6 byte1,2,3 */
-
- volatile u8 ccs_sleep_enable;/* MBAR_CDM + 0x1c reg7 byte0 */
- volatile u8 osc_sleep_enable;/* MBAR_CDM + 0x1d reg7 byte1 */
- volatile u8 reserved1; /* MBAR_CDM + 0x1e reg7 byte2 */
- volatile u8 ccs_qreq_test; /* MBAR_CDM + 0x1f reg7 byte3 */
-
- volatile u8 soft_reset; /* MBAR_CDM + 0x20 u8 byte0 */
- volatile u8 no_ckstp; /* MBAR_CDM + 0x21 u8 byte0 */
- volatile u8 reserved2[2]; /* MBAR_CDM + 0x22 u8 byte1,2,3 */
-
- volatile u8 pll_lock; /* MBAR_CDM + 0x24 reg9 byte0 */
- volatile u8 pll_looselock; /* MBAR_CDM + 0x25 reg9 byte1 */
- volatile u8 pll_sm_lockwin; /* MBAR_CDM + 0x26 reg9 byte2 */
- volatile u8 reserved3; /* MBAR_CDM + 0x27 reg9 byte3 */
-
- volatile u16 reserved4; /* MBAR_CDM + 0x28 reg10 byte0,1 */
- volatile u16 mclken_div_psc1;/* MBAR_CDM + 0x2a reg10 byte2,3 */
-
- volatile u16 reserved5; /* MBAR_CDM + 0x2c reg11 byte0,1 */
- volatile u16 mclken_div_psc2;/* MBAR_CDM + 0x2e reg11 byte2,3 */
-
- volatile u16 reserved6; /* MBAR_CDM + 0x30 reg12 byte0,1 */
- volatile u16 mclken_div_psc3;/* MBAR_CDM + 0x32 reg12 byte2,3 */
-
- volatile u16 reserved7; /* MBAR_CDM + 0x34 reg13 byte0,1 */
- volatile u16 mclken_div_psc6;/* MBAR_CDM + 0x36 reg13 byte2,3 */
+ u32 jtag_id; /* CDM + 0x00 reg0 read only */
+ u32 rstcfg; /* CDM + 0x04 reg1 read only */
+ u32 breadcrumb; /* CDM + 0x08 reg2 */
+
+ u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
+ u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
+ u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
+ u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
+
+ u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
+ u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
+ u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
+
+ u32 clk_enables; /* CDM + 0x14 reg5 */
+
+ u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
+ u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
+
+ u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
+ u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
+ u8 reserved1; /* CDM + 0x1e reg7 byte2 */
+ u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
+
+ u8 soft_reset; /* CDM + 0x20 u8 byte0 */
+ u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
+ u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
+
+ u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
+ u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
+ u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
+ u8 reserved3; /* CDM + 0x27 reg9 byte3 */
+
+ u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
+ u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
+
+ u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
+ u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
+
+ u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
+ u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
+
+ u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
+ u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */