-extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
-extern void destroy_context(struct mm_struct *mm);
-
-extern void __tsb_context_switch(unsigned long pgd_pa,
- struct tsb_config *tsb_base,
- struct tsb_config *tsb_huge,
- unsigned long tsb_descr_pa);
-
-static inline void tsb_context_switch(struct mm_struct *mm)
-{
- __tsb_context_switch(__pa(mm->pgd),
- &mm->context.tsb_block[0],
-#ifdef CONFIG_HUGETLB_PAGE
- (mm->context.tsb_block[1].tsb ?
- &mm->context.tsb_block[1] :
- NULL)
-#else
- NULL
-#endif
- , __pa(&mm->context.tsb_descr[0]));
-}
-
-extern void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long mm_rss);
-#ifdef CONFIG_SMP
-extern void smp_tsb_sync(struct mm_struct *mm);
-#else
-#define smp_tsb_sync(__mm) do { } while (0)
-#endif
+/* Initialize a new mmu context. This is invoked when a new
+ * address space instance (unique or shared) is instantiated.
+ * This just needs to set mm->context to an invalid context.
+ */
+#define init_new_context(__tsk, __mm) \
+ (((__mm)->context.sparc64_ctx_val = 0UL), 0)
+
+/* Destroy a dead context. This occurs when mmput drops the
+ * mm_users count to zero, the mmaps have been released, and
+ * all the page tables have been flushed. Our job is to destroy
+ * any remaining processor-specific state, and in the sparc64
+ * case this just means freeing up the mmu context ID held by
+ * this task if valid.
+ */
+#define destroy_context(__mm) \
+do { spin_lock(&ctx_alloc_lock); \
+ if (CTX_VALID((__mm)->context)) { \
+ unsigned long nr = CTX_NRBITS((__mm)->context); \
+ mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
+ } \
+ spin_unlock(&ctx_alloc_lock); \
+} while(0)
+
+/* Reload the two core values used by TLB miss handler
+ * processing on sparc64. They are:
+ * 1) The physical address of mm->pgd, when full page
+ * table walks are necessary, this is where the
+ * search begins.
+ * 2) A "PGD cache". For 32-bit tasks only pgd[0] is
+ * ever used since that maps the entire low 4GB
+ * completely. To speed up TLB miss processing we
+ * make this value available to the handlers. This
+ * decreases the amount of memory traffic incurred.
+ */
+#define reload_tlbmiss_state(__tsk, __mm) \
+do { \
+ register unsigned long paddr asm("o5"); \
+ register unsigned long pgd_cache asm("o4"); \
+ paddr = __pa((__mm)->pgd); \
+ pgd_cache = 0UL; \
+ if (task_thread_info(__tsk)->flags & _TIF_32BIT) \
+ pgd_cache = get_pgd_cache((__mm)->pgd); \
+ __asm__ __volatile__("wrpr %%g0, 0x494, %%pstate\n\t" \
+ "mov %3, %%g4\n\t" \
+ "mov %0, %%g7\n\t" \
+ "stxa %1, [%%g4] %2\n\t" \
+ "membar #Sync\n\t" \
+ "wrpr %%g0, 0x096, %%pstate" \
+ : /* no outputs */ \
+ : "r" (paddr), "r" (pgd_cache),\
+ "i" (ASI_DMMU), "i" (TSB_REG)); \
+} while(0)